Datasheet

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TMDS442 Read Phase 2:
Supply Voltage
TMDS Inputs
TMDS442
SLLS757A – AUGUST 2006 – REVISED MARCH 2007
Where each X logic state is defined by I2C-A1 and I2C-A0 pins being tied to either Vs+ or GND.
STEP 3 9
I
2
C Acknowledge (Slave) A
STEP 4 7 6 5 4 3 2 1 0
I
2
C Read Sink Port Address (Master) 0 0 0 0 0 0 Addr Addr
Where Addr is determined by the values shown in Table 2 .
STEP 5 9
I
2
C Acknowledge (Slave) A
STEP 6 0
I
2
C Stop (Master) P
STEP 7 0
I
2
C Start (Master) S
STEP 8 7 6 5 4 3 2 1 0
I
2
C General Address (Master) 0 1 0 1 1 X X 1
Where X logic state is defined by I2C-A1 and I2C-A0 pins being tied to either Vs+ or GND.
STEP 9 9
I
2
C Acknowledge (Slave) A
STEP 10 7 6 5 4 3 2 1 0
I
2
C Read Data (Slave) Data Data Data Data Data Data Data Data
Where Data is determined by the logic values contained in the Sink Port Register.
STEP 11 9
I
2
C Not-Acknowledge (Master) A
STEP 12 0
I
2
C Stop (Master) P
All V
CC
pins can be tied to a single 3.3-V power source. A 0.01- μ F capacitor is connected from each V
CC
pin
directly to ground to filter supply noise.
Standard TMDS terminations are integrated on all TMDS inputs. External terminations are not required. Each
input channel contains an 8-dB equalization circuit to compensate for cable losses. The voltage at the TMDS
input pins must be limited per the absolute maximum ratings. An unused input should not be connected to
ground as this would result in excessive current flow damaging the device. TMDS input pins do not incorporate
failsafe circuits. An unused input channel can be externally biased to prevent output oscillation. The
complementary input pin is recommended to be grounded through a 1-k Ω resistor and the other pin left open.
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