Datasheet

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Example - Reading From the TMDS442
TMDS Read Phase 1:
TMDS442
SLLS757A – AUGUST 2006 – REVISED MARCH 2007
STEP 1 0
I
2
C Start (Master) S
STEP 2 7 6 5 4 3 2 1 0
I
2
C General Address (Master) 0 1 0 1 1 X X 0
Where each X logic state is defined by I2C-A1 and I2C-A0 pins being tied to either Vs+ or GND.
STEP 3 9
I
2
C Acknowledge (Slave) A
STEP 4 7 6 5 4 3 2 1 0
I
2
C Write Sink Port Address (Master) 0 0 0 0 0 0 Addr Addr
Where Addr is determined by the values shown in Table 2 .
STEP 5 9
I
2
C Acknowledge (Slave) A
STEP 6 7 6 5 4 3 2 1 0
I
2
C Write Data (Master) Data Data Data Data Data Data Data Data
Where Data is determined by the values shown in Table 3 .
STEP 7 9
I
2
C Acknowledge (Slave) A
STEP 8 0
I
2
C Stop (Master) P
For step 4, an example of the proper bit control for selecting sink port 2 is 0000 0010.
For step 6, an example of the proper bit control for selecting source port B, enabling TMDS outputs and DDC link
of the sink port 2 without 3.5dB de-emphasis is 0000 1001.
The read operation consists of two phases. The first phase is the address phase. In this phase, an I
2
C master
initiates a write operation to the TMDS442 by generating a start condition (S) followed by the TMDS442 I
2
C
address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the
TMDS442, the master presents the sub-address (sink port) of the register it wants to read. After the cycle is
acknowledged (A), the master terminates the cycle immediately by generating a stop condition (P).
The second phase is the data phase. In this phase, an I
2
C master initiates a read operation to the TMDS442 by
generating a start condition followed by the TMDS442 I
2
C address (as shown below for a read operation), in
MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the TMDS442, the I
2
C
master receives one byte of data from the TMDS442. After the data byte has been transferred from the
TMDS442 to the master, the master generates a NOT-acknowledge followed by a stop. Similar to the write
function, to read both sink ports steps 1 through 11 must be repeated for each and every sink port desired.
STEP 1 0
I
2
C Start (Master) S
STEP 2 7 6 5 4 3 2 1 0
I
2
C General Address (Master) 0 1 0 1 1 X X 0
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