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A =No Acknowledge(SDA High)
A = Acknowledge
S=StartCondition
P =StopCondition
W=Write
R=Read
A
A A PDATA DATA
S Slave Address
FromTransmitter
FromReceiver
W
A6
A5
2
A0
A1
ACK
Acknowledge
(FromReceiver)
ICDevice Addressand
Read/WriteBit
R/W D7
D6 D0 D0
ACK
Stop
Condition
Acknowledge
(Receiver)
LastDataByte
SDA
D7
D6
D1 D1
FirstData
Byte
Start
Condition
Acknowledge
(Transmitter)
ACK
Other
DataBytes
A =No Acknowledge(SDA High)
A = Acknowledge
S=StartCondition
P =StopCondition
W=Write
R=Read
A
A A PDATA DATA
S Slave Address
Transmitter
Receiver
R
A6
2
A0
ACK
Acknowledge
(From
Receiver)
ICDevice Addressand
Read/WriteBit
R/W D7
D0
ACK
Stop
Condition
Acknowledge
(From
Transmitter)
LastDataByte
SDA
D7
D6
D1
D0
ACK
FirstData
Byte
Start
Condition
Not
Acknowledge
(Transmitter)
Other
DataBytes
Slave Address
TMDS442
SLLS757A – AUGUST 2006 – REVISED MARCH 2007
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 29 and Figure 30 .
Note that the TMDS442 does not allow multiple read transfers to occur. See Example – Reading from the
TMDS442 section for more information.
Figure 27. I
2
C Write Cycle
Figure 28. Multiple Byte Write Transfer
Figure 29. I
2
C Read Cycle
Figure 30. Multiple Byte Read Transfer
Both SDA and SCL must be connected to a positive supply voltage via a pull-up resistor. These resistors should
comply with the I
2
C specification that ranges from 2 k Ω to 19 k Ω . When the bus is free, both lines are high. The
address byte is the first byte received following the START condition from the master device. The first 5 Bits
(MSBs) of the address are factory preset to 01011. The next two bits of the TMDS442 address are controlled by
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