Datasheet

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SCL

SDA

DataLine

Stable;

DataValid

ChangeofData Allowed

Start

Condition

ClockPulsefor

Acknowledgement

Acknowledge

Not Acknowledge

DataOutput

byReceiver

DataOutput

byTransmitter

SCL From

Master

1 2

8 9

SCL

SDA

MSB

Slave Address Data

Stop

1 2 3 4 5 6 7 8 99 1 2 3 4 5 6 7 8 9

Acknowledge Acknowledge

TMDS442

SLLS757A – AUGUST 2006 – REVISED MARCH 2007

Figure 24. I

C Bit Transfer

Figure 25. I

C Acknowledge

Figure 26. I

C Address and Data Cycles

During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle so

that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the

receiving device will pull the SDA line low for one SCL clock cycle. A stop condition will be initiated by the

transmitting device after the last byte is transferred. An example of a write cycle can be found in Figure 27 and

Figure 28 . Note that the TMDS442 does not allow multiple write transfers to occur. See Example – Writing to the

TMDS442 section for more information.

During a read cycle, the slave receiver will acknowledge the initial address byte if it decodes the address as its

address. Following this initial acknowledge by the slave, the master device becomes a receiver and

Product Folder Link(s): TMDS442