Datasheet

TMDS361B
www.ti.com SLLS988A –SEPTEMBER 2009– REVISED JULY 2011
DISSIPATION RATINGS
DERATING FACTOR
(1)
T
A
= 70°C
PACKAGE PCB JEDEC STANDARD T
A
≤ 25°C
ABOVE T
A
= 25°C POWER RATING
Low-K 1066 mW 10.66 mW/°C 586 mW
64-pin TQFP (PAG)
High-K 1481 mW 14.8 mW/°C 814 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX
(1)
UNIT
R
θJB
Junction-to-board thermal resistance 37.13 °C/W
R
θJC
Junction-to-case thermal resistance 15.3 °C/W
LP = HIGH, TMDS: V
ID(pp)
= 1200 mV, 3 Gbps
P
D(1)
Device power dissipation in normal mode TMDS data pattern; HPD_SINK = HIGH, 560 780 mW
S1/S2 = LOW/LOW, LOW/HIGH, HIGH/HIGH
LP = HIGH, TMDS: V
ID(pp)
= 1200 mV, 3 Gbps
Device power dissipation in standby
P
D(2)
TMDS data pattern; HPD_SINK = HIGH, 10 20 mW
mode
S1 = HIGH, S2 = LOW
Device power dissipation in low-power
P
SD
LP = LOW 1 2 mW
mode
LP = HIGH, no TMDS input clock,
Device power dissipation in normal mode
P
NCLK
HPD_SINK =HIGH, S1/S2 = LOW/LOW, 40 65 mW
with no active TMDS input clock
LOW/HIGH, HIGH/HIGH
T
J
Junction Temperature 0 125 °C
(1) The maximum rating is simulated under 3.6-V VCC across worst-case temperature and process variation. Typical conditions are
simulated at 3.3-V VCC, 25°C with nominal process material.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
T
A
Operating free-air temperature 0 70 °C
TMDS DIFFERENTIAL OUTPUT AND INPUT PINS
V
ID(pp)
Peak-to-peak input differential voltage 0.15 1.56 V
V
IC
Input common-mode voltage VCC – 0.4 VCC + 0.01 V
t
IN_Rise_Fall
TMDS input rise and fall time 75 ps
Acceptable pre-emphasis on TMDS input signals. Note that an input
V
IN_PRE
signal into TMDS361B with longer pre-emphasis duration and/or larger See (Figure 26)
pre-emphasis amplitude could result in over-equalization.
AVCC TMDS output termination voltage 3 3.3 3.6 V
d
R
Data rate 3 Gbps
R
VSadj
Resistor for TMDS-compliant voltage output swing 3.66 4.02 4.47 kΩ
R
T
Termination resistance 45 50 55 Ω
DDC PINS
V
I
Input voltage 0 5.5 V
d
R(I2C)
I
2
C data rate 100 Kbps
HPD AND CONTROL PINS
V
IH
High-level input voltage 2 5.5 V
V
IL
Low-level input voltage 0 0.8 V
Copyright © 2009–2011, Texas Instruments Incorporated 9