Datasheet
TMDS361B
SLLS988A –SEPTEMBER 2009–REVISED JULY 2011
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Table 8. I
2
C Register 0x01 Lookup Table (continued)
BIT VALUE STATE DEFAULT DESCRIPTION
3:2 Bit 3 Bit 2 Output Edge Rate Control
1 1 Fastest TMDS output rise- and fall-time setting + 120 ps approximately (slowest rise- and
fall-time setting)
1 0 Fastest TMDS output rise- and fall-time setting + 100 ps approximately
0 1 Fastest TMDS output rise- and fall-time setting + 50 ps approximately
0 0 X Fastest TMDS output rise- and fall-time setting
1:0 Bit 1 Bit 0 Power Mode
1 0 Device enters low-power mode.
1 1 Device enters low-power mode.
0 1 Reserved
0 0 X Device is in normal-power mode.
Register 0x01 is read/write.
Table 9. I
2
C Register 0x02 Lookup Table
BIT VALUE STATE DEFAULT DESCRIPTION
7:6 Bit 7 Bit 6 Port Select Status Indicator
1 1 X Indicates port 1 is selected as the active port, all other ports are low.
1 0 Indicates port 2 is selected as the active port, all other ports are low.
0 0 Indicates port 3 is selected as the active port, all other ports are low.
0 1 Indicates standby mode: HPD[1:3] follow HPD_SINK.
5:4 Bit 4 Bit 3 OVS Control Status Indicator
0 0 Indicates DDC sink side V
OL
and V
IL
offset range 2: V
IL2 (max)
: 0.4 V, V
OL2 (max)
: 0.6 V
0 1 X Indicates DDC sink side V
OL
and V
IL
offset range 3: V
IL3 (max)
: 0.3 V, V
OL3 (max)
: 0.5 V
1 1 Indicates DDC sink side V
OL
and V
IL
offset range 1: V
IL1 (max)
: 0.4 V, V
OL1 (max)
: 0.7 V
3:2 Bit 3 Bit 2 Output Edge Rate Status Control
1 1 Indicates fastest TMDS output rise- and fall-time setting + 120 ps approximately (slowest rise
and fall time setting)
1 0 Indicates fastest TMDS output rise- and fall-time setting + 100 ps approximately
0 1 Indicates fastest TMDS output rise- and fall-time setting + 50 ps approximately
0 0 X Indicates fastest TMDS output rise- and fall-time setting
1:0 Bit 1 Bit 0 Power Mode Status Indicator
1 0 Indicates device enters low-power mode
1 1 Indicates device enters low-power mode
0 1 Reserved
0 0 X Indicates device is in normal-power mode
Register 0x02 is read-only.
Table 10. I
2
C Register 0x03 Lookup Table
BIT VALUE STATE DEFAULT DESCRIPTION
7 1 Clock Clock-detect circuit disabled. For HDMI compliance testing (TMDS termination-voltage test), the
detect clock-detect feature should be disabled. In this mode, the terminations on the TMDS input data
disabled lines are always connected when the port is selected.
0 Clock X Clock-detect circuit enabled. It is recommended that TMDS361B is used in this default mode
detect during normal operation where the clock detect circuit is enabled. The terminations on the
enabled TMDS input data lines are connected only when a valid TMDS clock is detected on the selected
port.
6:5 X RSVD Reserved
4 0 RSVD X Note: Do not write a 1 to this bit.
3:0 0 RSVD X Reserved
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