Datasheet

HPD_SINK
V
cc
R
INT
Clock Detect
R
INT
V
cc
R
INT
TMDS Rx
R
INT
V
cc
R
INT
Clock Detect
R
INT
V
cc
R
INT
TMDS Rx
R
INT
Dx+_1
Dx–_1
CLK+_1
CLK–_1
Dx+_3
Dx–_3
CLK+_3
CLK–_3
xx2
Rx
Tx
Rx
Tx
SCL1
SDA1
Rx
Tx
Rx
Tx
SCL3
SDA3
HPD1
1kW
HPD2
HPD3
VSadj
Dx+_SINK
Dx–_SINK
CLK+_SINK
CLK–_SINK
TMDS Tx
TMDS Tx
Tx
Rx
Tx
Rx
SDA_SINK
SCL_SINK
S1/SCL
S2/SDA
I2C_SEL
Clock Detect
LP
TMDS Rx
w/ AEQ
TMDS Rx
w/ AEQ
1kW
1kW
3:1
MUX
LocalI C
and
ControlLogic
2
B0330-01
TMDS361B
www.ti.com SLLS988A –SEPTEMBER 2009– REVISED JULY 2011
are four settings of the rise and fall times that can be chosen. The default setting is the fastest rise and fall
time; the other three settings are slower. Slower edge transitions can potentially help the sink system (HDTV)
in passing regulatory EMI compliance.
FUNCTIONAL BLOCK DIAGRAM
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