Datasheet

TMDS361B
SLLS988A –SEPTEMBER 2009–REVISED JULY 2011 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
When any of the input ports are selected, the integrated terminations (50-Ω termination resistors pulled up to
VCC) are switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC
repeater is enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines
are enabled, and the output TMDS lines are enabled. When an input port is not selected, the integrated
terminations are switched off, the TMDS receivers are disabled, and the DDC repeater is disabled.
Clock-detection circuitry provides an automatic power-management feature, because if no valid TMDS clock is
detected, the terminations on the input TMDS data lines are disconnected and the TMDS outputs are placed in a
high-impedance state.
The TMDS361B is designed to be controlled via a local I
2
C interface or GPIO interface based on the status of
the I2C_SEL pin. The local I
2
C interface in TMDS361B is a slave-only I
2
C interface. (See the I2C INTERFACE
NOTES section.)
I
2
C Mode: When the I2C_SEL pin is set low, the device is in I
2
C mode. With local I
2
C, the interface port status
can be read and the advanced configurations of the device such as TMDS output edge rate control, DDC I
2
C
buffer output-voltage-select (OVS) settings (See the DDC I2C Function Description for detailed description on
DDC I
2
C buffer description and OVS description), device power management, TMDS clock-detect feature, and
TMDS input-port selection can be set. See Table 8 through Table 11.
GPIO mode: When the I2C_SEL pin is set high, the device is in GPIO control mode. The port selection is
controlled with source selectors, S1 and S2. The power-saving mode is controlled through the LP pin. In GPIO
mode, the default TMDS output edge rate that is the fastest setting of rise and fall time is set, and the default
DDC I
2
C buffer OVS setting (OVS3) is set. See Table 8 and the DDC I2C Function Description for a detailed
description of the DDC I
2
C buffer.
Following are some of the key features (advantages) that TMDS361B provides to the overall sink-side system
(HDTV).
• 3×1 switch that supports TMDS data rates up to 3 Gbps on all three input ports
• ESD: Built-in support for high ESD protection (up to 10 kV on the HDMI source side). The HDMI source-side
pins on the TMDS361B are connected via the HDMI/DVI exterior connectors and cable to the HDMI/DVI
sources (e.g., DVD player). In TV applications, it can be expected that the source side may be subjected to
higher ESD stresses compared to the sink side that is connected internally to the HDMI receiver.
• Adaptive equalization: The built-in adaptive equalization support compensates for intersymbol interference
[ISI] loss of up to 20 dB, which represents a typical 20-m HDMI/DVI cable at 3 Gbps. Adaptive equalization
adjusts the equalization gain automatically, based on the cable length and the incoming TMDS data rate.
• TMDS clock-detect circuitry: This feature provides an automatic power-management feature and also ensures
that the TMDS output port is turned on only if there is a valid TMDS input signal. TMDS clock-detect feature
can be bypassed in I
2
C mode; see Table 10 and Table 11. It is recommended to enable the TMDS
clock-detect circuitry during normal operation. However, for HDMI compliance testing (TMDS
termination-voltage test), the clock-detect feature should be disabled by using the I
2
C mode control. If the
customer requires passing the TMDS termination-voltage test in GPIO mode with the default TMDS
clock-detect circuitry enabled, then a valid TMDS clock should be provided for this compliace test, so that the
terminations on the TMDS data pair can be connected, and thus customer can pass the TMDS
termination-voltage test.
• DDC I
2
C buffer: This feature provides isolation on the source side and sink side DDC I
2
C capacitance, thus
helping the sink system to pass system-level compliance.
• Robust TMDS receive stage: This feature ensures that the TMDS361B can work with TMDS input signals
having common-mode voltage levels that can be either compliant or non-compliant with HDMI/DVI
specifications.
• VSadj: This feature adjusts the TMDS output swing and can help the sink system to tune the output TMDS
swing of the TMDS361B (if needed) based on the system requirements.
• GPIO or local I
2
C interface to control the device features
• TMDS output edge-rate control: This feature adjusts the TMDS361B TMDS output rise and fall times. There
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