Datasheet

V
CC
AV
CC
50 W
50 W
50 W
50 W
0.5pF
V
Y
V
Z
Y
Z
Driver
Receiver
D+
D–
V
ID
V
D+
V
D–
V
ID
=V – V
D+ D–
(V +V )
D+ D–
2
V
ICM
=
V
OD
=V – V
Y Z
(V +V )
Y Z
2
V
OC
=
S0371-01
TMDS361B
SLLS988A –SEPTEMBER 2009–REVISED JULY 2011 www.ti.com
SWITCHING CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
AVCC = 3.3 V, R
T
= 50 Ω, input TMDS clock
frequency = 225 MHz. See Figure 14for
measurement setup; residual jitter is the total
jitter measured at TTP4 minus the jitter
t
JITC(PP)
Peak-to-peak output residual clock jitter 54 84 ps
measured at TTP1. See Figure 15 for the loss
profile of the cable used for t
JITC(PP)
measurement. t
JITC(PP)
is measured at TMDS
differential clock signal crossing.
t
CLK1
Valid clock-detect enable time AVCC = 3.3 V, R
T
= 50 Ω, input TMDS clock 300 500 ns
frequency = 300 MHz. See Figure 13.
t
CLK2
Invalid clock-detect disable time AVCC = 3.3 V, R
T
= 50 Ω, input TMDS clock 500 800 ns
frequency = 1 MHz. See Figure 13.
t
SEL1
Port selection time (see
(4)
AVCC = 3.3 V, R
T
= 50 Ω 300 500 ns
t
SEL2
Port deselection time (see
(5)
) AVCC = 3.3 V, R
T
= 50 Ω 40 50 ns
f
CD
Clock-detect frequency AVCC = 3.3 V, R
T
= 50 Ω. See Figure 13. 25 300 MHz
(4) t
SEL1
includes the time for the valid clock-detect enable time and t
S1(HPD)
, because the t
S1(HPD)
event happens in parallel with t
SEL1
; thus,
the t
SEL1
time is primarily the t
CLK1
time.
(5) t
SEL2
is primarily the t
S2(HPD)
time.
Figure 9. TMDS Main-Link Test Circuit
16 Copyright © 2009–2011, Texas Instruments Incorporated