Datasheet

TMDS361B
www.ti.com SLLS988A –SEPTEMBER 2009– REVISED JULY 2011
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
Single-ended HIGH-level output voltage AVCC – 10 AVCC + 10 mV
V
OL
Single-ended LOW-level output voltage AVCC – 600 AVCC – 400 mV
V
SWING
Single-ended output voltage swing 400 600 mV
AVCC = 3.3 V, R
T
= 50 Ω
Change in steady-state common-mode
V
OC(SS)
5 mV
output voltage between logic states
V
OD(pp)
Peak-to-peak output differential voltage 800 1200 mV
V
(O)SBY
Single-ended standby output voltage AVCC – 10 AVCC + 10 mV
0 V ≤ VCC ≤ 1.5 V, AVCC = 3.3 V,
I
(O)OFF
Single-ended power-down output current –10 10 μA
R
T
= 50 Ω
I
OS
Short-circuit output current See Figure 16 -15 12 15 mA
Minimum valid clock differential voltage Input TMDS clock frequency = 300
V
CD(pp)
100 mV
(peak-to-peak) MHz
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time 250 800 ps
t
PHL
Propagation delay time 250 800 ps
t
R1
Rise time, fastest mode (default 84 110 140 ps
setting): fastest setting
t
F1
Fall time, fastest mode (default setting): 84 110 140 ps
fastest setting
t
R2
Rise time, fastest mode + 50 ps 142 160 190 ps
(approximately)
t
F2
Fall time, fastest mode + 50 ps 142 160 190 ps
AVCC = 3.3 V, R
T
= 50 Ω. See Figure 9 and
(approximately)
Figure 10.
t
R3
Rise time, fastest mode + 100 ps 187 210 230 ps
(approximately)
t
F3
Fall time, fastest mode + 100 ps 187 210 230 ps
(approximately)
t
R4
Rise time, fastest mode + 120 ps 216 230 260 ps
(approximately): slowest setting
t
F4
Fall time, fastest mode + 120 ps 216 230 260 ps
(approximately): slowest setting
t
SK(P)
Pulse skew (see
(2)
) 8 15 ps
t
SK(D)
Intra-pair skew AVCC = 3.3 V, R
T
= 50 Ω. See Figure 11. 10 30 ps
t
SK(O)
Inter-pair skew (see
(3)
) 100 ps
AVCC = 3.3 V, R
T
= 50 Ω, dR = 2.25 Gbps.
See Figure 14 for measurement setup; residual
jitter is the total jitter measured at TTP4 minus
the jitter measured at TTP1. See Figure 15 for
t
JITD(PP)
Peak-to-peak output residual data jitter 125 198 ps
the loss profile of the cable used for t
JITD(PP)
measurement. Also see Typical Curves for
t
JITD(PP)
across cable length and input TMDS
data rate.
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) t
sk(p)
is the magnitude of the time difference between t
PLH
and t
PHL
of a specified terminal.
(3) t
sk(o)
is the magnitude of the difference in propagation delay times between any specified terminals of a sink-port bank when inputs of
the active source port are tied together.
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