Datasheet
TMDS351
www.ti.com
SLLS840B –MAY 2007– REVISED JULY 2011
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
DDC I/O PINS
I
lkg
Input leakage current V
I
= 0.1 V
DD
to 0.9 V
DD
to isolated DDC inputs -10 10 µA
C
IO
Input/output capacitance V
I(pp)
= 1 V, 100 kHz 10 pF
R
ON
Switch resistance I
O
= 3 mA, V
O
= 0.4 V 27 40 Ω
V
PASS
Switch output voltage V
I
= 5 V, I
O
= 100 µA 1.9 3.6 V
STATUS AND SOURCE SELECTOR PINS
I
IH
High-level digital input current V
IH
= 2 V or V
DD
-10 10 µA
I
IL
Low-level digital input current V
IL
= GND or 0.8 V -10 10 µA
V
OH
TTL High-level output voltage I
OH
= –100 μA 2.4 V
DD
V
V
OL
TTL Low-level output voltage I
OL
= 100 μA GND 0.4 V
SWITCHING CHARACTERISTICS
(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(2)
MAX UNIT
TMDS DIFFERENTIAL PINS (Y/Z)
t
PLH
Propagation delay time, low-to-high-level output 400 650 900 ps
t
PHL
Propagation delay time, high-to-low-level output 400 650 900 ps
t
r
Differential output signal rise time (20% - 80%) 60 80 140 ps
t
f
Differential output signal fall time (20% - 80%) 60 80 140 ps
See Figure 2, AV
CC
= 3.3 V,
R
T
= 50 Ω, PRE = 0 V
t
sk(p)
Pulse skew (|t
PHL
– t
PLH
|)
(3)
6 20 ps
t
sk(D)
Intra-pair differential skew, see Figure 4 20 40 ps
t
sk(o)
Inter-pair channel-to-channel output skew
(4)
30 65 ps
t
sk(pp)
Part-to-part skew
(5)
510 ps
t
jit(pp)
Peak-to-peak output jitter from Yj/Zj(1) residual jitter See Figure 5, 8 20 ps
Am/Bm(1) = 250 MHz clock,
t
jit(pp)
Peak-to-peak output jitter from Yj/Zj(2:4) residual jitter 60 80 ps
Am/Bm(2:4) = 2.5 Gbps HDMI pattern
t
SX
Select to switch output 50 70 ns
See Figure 6,
t
en
Enable time 170 250 ns
10-mA Current source to the input
t
dis
Disable time 9 15 ns
Propagation delay from SCLn to SCL_SINK or SDAn to
t
pd(DDC)
8 15 ns
SDA_SINK or SDA_SINK to SDAn
t
sx(DDC)
Switch time from SCLn to SCL_SINK 8 15 ns
See Figure 7, C
L
= 10 pF
t
pd(HPD)
Propagation delay (from HPD_SINK to the active port of HPD) 14 20 ns
t
sx(HPD)
Switch time from port select to the latest valid status of HPD 33 50 ns
(1) Measurements are made with the Agilent 81250 ParBert System with a N4872A generator (600 fs t
JIT(CLK)
, 13 ps t
JIT(pp)
) and a N4873A
analyzer.
(2) All typical values are at 25°C and with a 3.3-V supply.
(3) t
sk(p)
is the magnitude of the time difference between t
PLH
and t
PHL
of a specified terminal.
(4) t
sk(o)
is the magnitude of the difference in propagation delay times between any specified terminals of a sink-port bank when inputs of
the active source port are tied together.
(5) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same source, the same supply voltages, at the same temperature, and have identical packages and test circuits.
Copyright © 2007–2011, Texas Instruments Incorporated 9