Datasheet

Start
Condition
SDA
Acknowledge
(FromReceiver)
Acknowledge
(From Transmitter)
Not Acknowledge
(Transmitter)
Stop
Condition
LastDataByte
I CDevice Addressand
Read/WriteBit
2
FirstData
Byte
Other
DataBytes
A6 A0
ACK
R/W D7
D0
ACK
D7 D6 D1 D0
ACK
T0398-01
TMDS261B
SLLS987A –SEPTEMBER 2009–REVISED JULY 2011 www.ti.com
Figure 57. Multiple-Byte Read Transfer
Slave Address
Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. These resistors should
comply with the I
2
C specification that ranges from 2 kΩ to 19 kΩ. When the bus is free, both lines are high. The
address byte is the first byte received following the START condition from the master device. The 7-bit address is
factory preset to 0101 100. Table 7 lists the calls that the TMDS261B responds to.
Table 7. TMDS261B Slave Address
FIXED ADDRESS READ/WRITE BIT
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (R/W)
0 1 0 1 1 0 0 1/0
EXAMPLE – WRITING TO THE TMDS261B
The proper way to write to the TMDS261B is illustrated as follows:
An I
2
C master initiates a write operation to the TMDS261B by generating a start condition (S) followed by the
TMDS261B I
2
C address (as shown following, in MSB-first bit order, followed by a 0 to indicate a write cycle. After
receiving an acknowledge from the TMDS261B, the master presents the subaddress (sink port) to be written,
consisting of one byte of data, MSB-first. The TMDS261B acknowledges the byte after completion of the transfer.
Finally, the master presents the data to be written to the register (sink port), and the TMDS261B acknowledges
the byte. The master can continue presenting data to be written after TMDS261B acknowledges the previous
byte (steps 6, 7). After the last byte to be written has been acknowledged by TMDS261B, the I
2
C master then
terminates the write operation by generating a stop condition (P).
Step 1 0
I
2
C start (master) S
Step 2 7 6 5 4 3 2 1 0
I
2
C general address (master) 0 1 0 1 1 0 0 0
Step 3 8
I
2
C acknowledge (slave) A
Step 4 7 6 5 4 3 2 1 0
I
2
C write sink logic address (master) 0 0 0 0 Addr Addr Addr Addr
Step 5 8
I
2
C acknowledge (slave) A
Step 6 7 6 5 4 3 2 1 0
I
2
C write data (master) Data Data Data Data Data Data Data Data
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