Datasheet

SCL
SDA
MSB
Slave Address
Acknowledge
Data
Acknowledge
Stop
123456789123456789
T0396-01
S Slave Address
W A
Data
A
Data
A P
FromReceiver
From Transmitter
A =No Acknowledge(SDA High)
A = Acknowledge
S=StartCondition
P =StopCondition
W=Write
R0007-01
Acknowledge
(FromReceiver)
Start
Condition
Acknowledge
(Receiver)
Acknowledge
(Receiver)
SDA
Stop
Condition
I CDevice Addressand
Read/WriteBit
2
FirstDataByte
Other
DataBytes
LastDataByte
A6
ACK
A5 A1 A0 R/W D7 D6 D1 D0
ACK
D7 D6 D1 D0
ACK
T0397-01
S Slave Address
R A
Data
A
Data
A
P
Receiver
Transmitter
A =No Acknowledge(SDA High)
A = Acknowledge
S=StartCondition
P =StopCondition
W=Write
R=Read
R0008-01
TMDS261B
www.ti.com SLLS987A –SEPTEMBER 2009– REVISED JULY 2011
Figure 53. I
2
C Address, Data Cycle(s), and Stop
During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle so
that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the
receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting
device after the last byte is transferred. An example of a write cycle can be found in Figure 54 and Figure 55.
Note that the TMDS261B allows multiple write transfers to occur. See the Example – Writing to the TMDS261
section for more information.
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not-acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 56 and Figure 57.
See the Example – Reading from the TMDS261 section for more information.
Figure 54. I
2
C Write Cycle
Figure 55. Multiple-Byte Write Transfer
Figure 56. I
2
C Read Cycle
Copyright © 2009–2011, Texas Instruments Incorporated 37