Datasheet

SINK
HDMI RX
DDC_SDA
DDC_SCL
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
3.3V
4.7kW 4.7kW
4.02kW 10%
mController
HPDx
SDAx
SCLx
Ax1/Bx1
Ax2/Bx2
Ax3/Bx3
Ax4/Bx4
EQ
S1
S2
HPD_SINK
SDA_SINK
SCL_SINK
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
VSadj
VDD
(5V)
VCC
(3.3V)
GND
SDA SCL
CEC
LOGIC
CEC
PHY
1kW
5V
47kW
CEC
E-EDID
1kW
HPD
5V
SDA
SCL
CEC
CLK
D0
D1
D2
HPD
5V
SDA
SCL
CEC
CLK
D0
D1
D2
SOURCE
in general HDMI output
S
Start
Condition
Stop
Condition
P
SDA
SCL
SDA
SCL
T0393-01
TMDS261B
www.ti.com SLLS987A –SEPTEMBER 2009– REVISED JULY 2011
Figure 49. Two-Port HDMI-Enabled DTV With TMDS261B – External Logic – CEC Commands Active
I
2
C INTERFACE NOTES
The I
2
C interface is used to access the internal registers of the TMDS261B. I
2
C is a two-wire serial interface
developed by Philips Semiconductor (see I
2
C-Bus Specification, Version 2.1, January 2000). The bus consists of
a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines
are pulled high. All the I
2
C-compatible devices connect to the I
2
C bus through open-drain I/O pins, SDA and
SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus
under control of the master device. The TMDS261B works as a slave and supports standard-mode transfer (100
kbps).
The basic I
2
C start and stop access cycles are shown in Figure 50.
The basic access cycle consists of the following:
• A start condition
• A slave address cycle
• Any number of data cycles
• A stop condition
Figure 50. I
2
C Start and Stop Conditions
Copyright © 2009–2011, Texas Instruments Incorporated 35