Datasheet
HPD_SINK
VCC
R
INT
Clock Detect
R
INT
VCC
R
INT
TMDS Rx
R
INT
VCC
R
INT
Clock Detect
R
INT
VCC
R
INT
TMDS Rx
R
INT
Dx+_1
Dx–_1
CLK+_1
CLK–_1
Dx+_2
Dx–_2
CLK+_2
CLK–_2
Rx
Tx
Rx
Tx
SCL1
SDA1
Rx
Tx
Rx
Tx
SCL2
SDA2
VSadj
Dx+_SINK
Dx–_SINK
CLK+_SINK
CLK–_SINK
TMDS Tx
TMDS Tx
Tx
Rx
Tx
Rx
SDA_SINK
SCL_SINK
S1/SCL
S2/SDA
I2C_SEL
Clock Detect
LP
TMDS Rx
w/ AEQ
TMDS Rx
w/ AEQ
HPD1
1kW
HPD2
1kW
2:1
MUX
LocalI C
and
ControlLogic
2
B0330-02
o
TMDS261B
www.ti.com
SLLS987A –SEPTEMBER 2009– REVISED JULY 2011
are four settings of the rise and fall times that can be chosen. The default setting is the fastest rise and fall
time; the other three settings are slower. Slower edge transitions can potentially help the sink system (HDTV)
in passing regulatory EMI compliance.
FUNCTIONAL BLOCK DIAGRAM
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