Datasheet

TMDS141
www.ti.com SLLS737D –JUNE 2006– REVISED SEPTEMBER 2011
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IH
= V
CC
, V
IL
= V
CC
– 0.4 V, R
T
= 50 Ω,
AV
CC
= 3.3 V, R
VSADJ
= 4.64 kΩ,
I
CC
Supply current 108 130
(2)
mA
1.65-Gbps HDMI data pattern,
165-MHz Pixel clock, PRE = Low
V
IH
= V
CC
, V
IL
= V
CC
– 0.4 V, R
T
= 50 Ω,
AV
CC
= 3.3 V, R
VSADJ
= 4.64 kΩ,
P
D
Power dissipation 497
(2)
mW
1.65-Gbps HDMI data pattern,
165-MHz Pixel clock, PRE = Low
TMDS DIFFERENTIAL PINS (TX, TXC)
V
OH
Single-ended high-level output voltage AV
CC
–10 AV
CC
+10 mV
V
OL
Single-ended low-level output voltage AV
CC
–600 AV
CC
–400 mV
V
swing
Single-ended output swing voltage 400 600 mV
See Figure 3, AV
CC
= 3.3 V,
V
OD(O)
Overshoot of output differential voltage 15% 2× V
swing
R
T
= 50 Ω
V
OD(U)
Undershoot of output differential voltage 25% 2× V
swing
Change in steady-state common-mode
ΔV
OC(SS)
5 mV
output voltage between logic states
0 V ≤ V
CC
≤ 1.5 V,
I
(O)OFF
Single-ended standby output current –10 10 µA
AV
CC
= 3.3 V, R
T
= 50 Ω
V
OD(pp)
Peak-to-peak output differential voltage 800 1200
See Figure 4, PRE = High,
mVp-p
Steady state output differential voltage
AV
CC
= 3.3 V, R
T
= 50 Ω
V
ODE(SS)
600 820
with de-emphasis
I
(OS)
Short circuit output current See Figure 5 -12 12 mA
Single-ended input voltage under high
V
I(open)
I
I
= 10 µA V
CC
–10 V
CC
+10 mV
impedance input or open input
R
INT
Input termination resistance V
IN
= 2.9 V 45 50 55 Ω
CONTROL PINS (PRE, OE, I2CEN, OVS)
|I
IH
| High-level digital input current V
IH
= 2 V or V
CC
-10 10 µA
|I
IL
| Low-level digital input current V
IL
= GND or 0.8 V -10 10 µA
I
2
C PINS (TSCL, TSDA)
V
I
= 5.5 V -50 50
|I
lkg
| Input leakage current µA
V
I
= V
CC
-10 10
|I
OH
| High-level output current V
O
= 3.6 V -10 10 µA
|I
IL
| Low-level input current V
IL
= GND -40 40 µA
OVS = NC
(3)
0.47 0.6
V
OL
Low-level output voltage I
OL
= 400 μA or 4 mA OVS = GND
(3)
0.6 0.75 V
OVS = V
CC
(3)
0.75 0.95
OVS = NC
(3)
70
Low-level input voltage below output
V
OL
-V
ILC
Ensured by design OVS = GND
(3)
220 mV
low-level voltage level
OVS = V
CC
(3)
370
V
I
= 5.0 V or 0 V, Freq = 100 kHz 25
C
IO
Input/output capacitance pF
V
I
= 3.0 V or 0 V, Freq = 100 kHz 10
I
2
C PINS (RSCL, RSDA)
V
I
= 5.5 V -50 50
|I
lkg
| Input leakage current μA
V
I
= V
CC
-10 10
|I
OH
| High-level output current V
O
= 3.6 V -10 10 µA
|I
IL
| Low-level input current V
IL
= GND -10 10 µA
V
OL
Low-level output voltage I
OL
= 4 mA 0.2 V
V
I
= 5.0 V or 0 V, Freq = 100 kHz 25
C
I
Input capacitance pF
V
I
= 3.0 V or 0 V, Freq = 100 kHz 10
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) The maximum rating is characterized under 3.6 V V
CC
and 600 mV V
ID
.
(3) The patent of the OVS pin is filed.
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