Datasheet
TMDS141
www.ti.com
SLLS737D –JUNE 2006– REVISED SEPTEMBER 2011
Table 2. Pull-Up Resistor Upon Different Threshold Voltages and 800-pF Loads
V
th-
\V
th+
0.7V
DD
0.65V
DD
0.6V
DD
0.55V
DD
0.5V
DD
0.45V
DD
0.4V
DD
0.35V
DD
0.3V
DD
UNIT
0.1V
DD
1.14 1.32 1.54 1.80 2.13 2.54 3.08 3.84 4.97 kΩ
0.15V
DD
1.20 1.41 1.66 1.97 2.36 2.87 3.59 4.66 6.44 kΩ
0.2V
DD
1.27 1.51 1.80 2.17 2.66 3.34 4.35 6.02 9.36 kΩ
0.25V
DD
1.36 1.64 1.99 2.45 3.08 4.03 5.60 8.74 18.12 kΩ
0.3V
DD
1.48 1.80 2.23 2.83 3.72 5.18 8.11 16.87 - kΩ
Or, limiting the maximum load capacitance of each cable to be 400 pF to accommodate with I
2
C spec version
2.1. C
cable(max)
= 400pF/C
source
=50pF/C
i
= 50pF, the maximum values of R
(max)
are calculated as shown in
Table 3.
Table 3. Pull-Up Resistor Upon Different Threshold Voltages and 500-pF Loads
V
th-
\V
th+
0.7V
DD
0.65V
DD
0.6V
DD
0.55V
DD
0.5V
DD
0.45V
DD
0.4V
DD
0.35V
DD
0.3V
DD
UNIT
0.1V
DD
1.82 2.12 2.47 2.89 3.40 4.06 4.93 6.15 7.96 kΩ
0.15V
DD
1.92 2.25 2.65 3.14 3.77 4.59 5.74 7.46 10.30 kΩ
0.2V
DD
2.04 2.42 2.89 3.48 4.26 5.34 6.95 9.63 14.98 kΩ
0.25V
DD
2.18 2.62 3.18 3.92 4.93 6.45 8.96 13.98 28.99 kΩ
0.3V
DD
2.36 2.89 3.57 4.53 5.94 8.29 12.97 26.99 - kΩ
Obviously, to accommodate the 3-mA drive current specification, a narrower threshold voltage range is required
to support a maximum 800-pF load capacitance for a standard-mode I
2
C bus.
When the input low and high level threshold voltages, V
th-
and V
th+
, are 0.7 V and 1.9 V, which is 0.15 V
DD
and
0.4 V
DD
approximately with V
DD
= 5 V, from Table 2, the maximum pull-up resistor is 3.59 kΩ. The allowable
pull-up resistor is in the range of 1.83 kΩ and 3.59 kΩ.
Thermal Dissipation
On a high-K board – It is always recommended to solder the PowerPAD™ onto the thermal land. A thermal land
is the area of solder-tinned-copper underneath the PowerPAD package. On a high-K board the TMDS141 can
operate over the full temperature range by soldering the PowerPAD onto the thermal land without vias.
On a low-K board – In order for the device to operate across the temperature range on a low-K board, a 1-oz Cu
trace connecting the GND pins to the thermal land must be used. A simulation shows R
θJA
= 100.84°C/W
allowing 545 mW power dissipation at 70°C ambient temperature.
A general PCB design guide for PowerPAD packages is provided in the document SLMA002 - PowerPAD
Thermally Enhanced Package.
Copyright © 2006–2011, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TMDS141