Datasheet

Master
Slave
DriverR
Driver T
V
Rdd
R
Rup
C
CABLE
C
SOURCE
C
I
C
O
C
slave
V
Tdd
R
Tup
C
medium
RSCL
RSDA
9thClockPulse- AcknowledgeFromSlave
TSCL
TSDA
9thClockPulse- AcknowledgeFromSlave
V
OL
OfSlave
V
OL
OfDriver T
TMDS141
www.ti.com SLLS737D –JUNE 2006– REVISED SEPTEMBER 2011
Figure 21. Typical Application
Figure 22 illustrates the waveforms seen on the R-side I
2
C-bus when the master writes to the slave through the
I
2
C repeater circuit of the TMDS141. This looks like a normal I
2
C transmission, and the turn on and turn off of the
acknowledge signals are slightly delayed.
Figure 22. Bus R Waveform
Figure 23 illustrates the waveforms seen on the T-side I
2
C-bus under the same operation in Figure 22. On the
T-side of the I
2
C repeater, the clock and data lines would have a positive offset from ground equal to the V
OL
of
the driver T. After the 8th clock pulse, the data line is pulled to the V
OL
of the slave device which is very close to
ground in this example. At the end of the acknowledge, the slave device releases and the bus level rises back to
the V
OL
set by the driver until the R-side rises above V
CC
/2, after which it continues to high. It is important to note
that any arbitration or clock stretching events require that the low level on the T-side bus at the input of the
TMDS141 I
2
C repeater is below 0.4 V to be recognized by the device and then transmitted to the R-side I
2
C bus.
Figure 23. Bus T Waveform
The I
2
C circuitry inside the TMDS141 allows multiple stage operation as shown in Figure 24. I
2
C-Bus slave
devices can be connected to any of the bus segments. The number of devices that can be connected in series is
limited by repeater delay/time of flight considerations for the maximum bus speed requirements.
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