Datasheet

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SLAS326A − JANUARY 2001 − REVISED MARCH 2004
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
CCD IN
SR
SV
ADCCLK
t
SRD
t
SVD
t
ADC_SV
TIMING PARAMETER
MIN TYP MAX EXPLANATION
t
SRD
Delay between sample reset (SR) rising edge and
actual sampling instant (ns)
6 This is the fixed internal delay in the chip. The reset
value of the CCD waveform should be stable until
the end of this period.
t
SVD
Delay between sample video (SV) rising edge and
actual instant of video signal sampling (ns)
6 This is the fixed internal delay in the chip. The video
signal value of the CCD waveform should be stable
until the end of this period.
t
ADC_SV
Time between ADCCLK falling edge and SV falling
edge
3 The timing margin required to ensure the ADCCLK
positive half cycle is in between two SV pulses
Figure 4. Detailed Internal Timing Diagram