Datasheet

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      
SLAS326A − JANUARY 2001 − REVISED MARCH 2004
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, T
A
= 25°C,
AV
DD
=DV
DD
=3 V, ADCCLK=40 MHz (unless otherwise noted)
user digital-to-analog converters (DAC)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DAC resolution 8 Bits
INL Integral nonlinearity ±0.75 LSB
DNL Differential nonlinearity ±0.5 LSB
Output voltage range 0 V
DD
V
Output settling time 10 pF external load, settle to 1 mV 4 µs
reference voltages
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal bandgap voltage reference 1.43 1.50 1.58 V
Temperature coefficient 100 ppm/°C
ADC Ref+
Externally decoupled
2 V
ADC Ref−
Externally decoupled
1 V
digital specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Logic inputs
I
IH
High-level input current
DIV
DD
= 3 V
−10 10
A
I
IL
Low-level input current
DIV
DD
= 3 V
−10 10
µA
C
i
Input capacitance 5 pF
Logic outputs
V
OH
High-level output voltage I
OH
= 50 µA, DIV
DD
= 3 V DIV
DD
−0.4 V
V
OL
Low-level output voltage I
OL
= 50 µA, DIV
DD
= 3 V 0.4 V
I
OZ
High-impedance-state output current ±10 µA
C
o
Output capacitance 5 pF
key timing requirements
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
SRW
SR pulse width
Measured at 50% of pulse height
10 ns
t
SVW
SV pulse width
Measured at 50% of pulse height
10 ns
t
OD
ADCCLK-to-output data delay 6 ns
t
CSF
CS falling edge to SCLK rising edge 0 ns
t
CSR
SCLK falling edge to CS rising edge 5 ns