Datasheet


      
SLAS326A − JANUARY 2001 − REVISED MARCH 2004
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, T
A
= 25°C,
AV
DD
=DV
DD
=3 V, ADCCLK=40 MHz (unless otherwise noted)
total device
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AV
DD
operating current 56 mA
DV
DD
operating current 8 mA
Device power consumption 200 mW
Power consumption in power-down mode 2 mW
INL Full channel integral nonlinearity
AV
DD
=DV
DD
= 2.7 V – 3.3 V,
Using best fit method
±1.75 ±2.15 LSB
DNL Full channel differential nonlinearity
AV
DD
=DV
DD
= 2.7 V – 3.3 V,
ADCCLK=18 MSPS, 10 bits
±0.5 ±0.99 LSB
No missing code Assured
Full channel output latency 6
CLK
cycles
analog-to-digital converter (ADC)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC resolution in CCD mode 10 Bits
Full scale input span 2 V
P-P
Conversion rate 40 MHz
correlated double sample (CDS) and programmable gain amplifier (PGA)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CDS and PGA sample rate 40 MHz
CDS full-scale input span Single-ended input 1 V
Input capacitance of CDS 4 pF
Minimum PGA gain 0 1 dB
Maximum PGA gain 35 36 37 dB
PGA gain resolution 0.045 dB
PGA programming code resolution 10 Bits
internal digital-to-analog converters (DAC) for offset correction
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DAC resolution 8 Bits
INL Integral nonlinearity ±0.5 LSB
DNL Differential nonlinearity ±0.5 LSB
Output settling time To 1% accuracy 80 ns