Datasheet
SLAS326A − JANUARY 2001 − REVISED MARCH 2004
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL I/O DESCRIPTION
NAME NO.
ADCCLK 25 I ADC clock input
AGND1 44 Analog ground for internal CDS circuits
AGND2 4 Analog ground for internal PGA circuits
AGND3 20 Analog ground for internal DAC circuits
AGND4 32 Analog ground for internal ADC circuits
AGND5 37 Analog ground for internal REF circuits
AV
DD1
43 Analog supply voltage for internal CDS circuits, 3 V
AV
DD2
3 Analog supply voltage for internal PGA circuits, 3 V
AV
DD3
19 Analog supply voltage for internal DAC circuits, 3 V
AV
DD4
33 Analog supply voltage for internal ADC circuits, 3 V
AV
DD5
41 Analog supply voltage for internal ADC circuits, 3 V
BLKG 36 I Control input. The CDS operation is disabled when BLKG is pulled low.
CLCCD 47 I CCD signal clamp control input
CCDIN 1 I CCD input
CLREF 48 O Clamp reference voltage output
CP 34, 35 I Connect this pin to AV
DD
.
CS 28 I Chip select. A logic low on this input enables the serial port.
D0 – D9 7–16 O 10-bit 3-state ADC output data or offset DACs test data
DACO1 21 O Digital-to-analog converter output1
DACO2 22 O Digital-to-analog converter output2
DGND 5 Digital ground
DIGND 18 Digital interface circuit ground
DIV
DD
17 Digital interface circuit supply voltage, 1.8 V− 4.4 V
DV
DD
6 Digital supply voltage, 3 V
NC 2 I Not connected
OBCLP 31 I Optical black level and offset calibration control input. Active low.
OE 24 I Output data enable. Active low.
RBD 38 O Internal bandgap reference for external decoupling
RESET 29 I Hardware-reset input, active low. This signal forces a reset of all internal registers
RMD 39 O Ref− output for external decoupling
RPD 40 O Ref+ output for external decoupling
SDIN 27 I Serial data input to configure the internal registers
SCKP 23 I Selects the polarity of SCLK. 0 – active low (high when SCLK is not running), 1 – active high (low when
SCLK is not running)
SCLK 26 I Serial clock input. This clock synchronizes the serial data transfer.
SR 45 I CCD reference level sample clock input
STBY 30 I Hardware power-down control input, active low
SV 46 I CCD signal level sample clock input
V
SS
42 Silicon substrate, normally connected to analog ground