Datasheet
SLAS326A − JANUARY 2001 − REVISED MARCH 2004
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
device reset
When pin RESET (pin 29) is pulled low, all internal registers are set to their default values. The device also resets
itself when it is first powered on. In addition, the TLV990-40 has a software-reset function that resets the device
when writing a control bit to the control register.
See the register definition section for the register default values.
voltage references
An internal precision-voltage reference of 1.5 V nominal is provided. This reference voltage is used to generate
the ADC Ref− voltage of 1 V and Ref+ of 2 V. It is also used to set the clamp voltage. All internally-generated
voltages are fixed values and cannot be adjusted.
power-down mode (standby)
The TLV990-40 implements both hardware and software power-down modes. Pulling pin STBY (pin 30) low
puts the device in the low-power standby mode. Total supply current drops to about 0.6 mA. Setting a
power-down control bit in the control register can also activate the power-down mode. The user can still program
all internal registers during the power-down mode.
power supply
The TLV990-40 has several power-supply pins. Each major internal analog block has a dedicated AV
DD
supply
pin. All internal digital circuitry is powered by DV
DD
. Both AV
DD
and DV
DD
are 3-V nominal.
The DIV
DD
and DIGND pins supply power to the output digital driver (D9−D0). The DIV
DD
is independent of the
DV
DD
and can be operated from 1.8 V to 4.4 V. This allows the outputs to interface with digital ASICs requiring
different supply voltages.
ground and decoupling
All ground pins of the TLV990-40 are not internally connected and must be connected externally to PCB ground.
General practices should apply to the PCB design to limit high-frequency transients and noise that are fed back
into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed.
In the case of power supply decoupling, 0.1-µF ceramic chip capacitors are adequate to keep the impedance
low over a wide frequency range. Recommended external decoupling for the three voltage-reference pins is
shown in Figure 4. Since their effectiveness depends largely on the proximity to the individual supply pin, all
decoupling capacitors should be placed as close as possible to the supply pins.
To reduce high-frequency and noise coupling, it is highly recommended that digital and analog grounds be
shorted immediately outside the package. This can be accomplished by running a low-impedance line between
DGND and AGND under the package.