Datasheet
SLAS326A − JANUARY 2001 − REVISED MARCH 2004
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
ADC
The ADC employs a pipelined architecture to achieve high throughput and low power consumption. Fully-
differential implementation and digital-error correction ensure 10-bit resolution.
The latency of the ADC data output is 6 ADCCLK cycles, as shown in Figure 1. Pulling the OE pin (pin 24) high
puts the ADC output in high impedance.
user DACs
The TLV990-40 includes two user DACs that can be used for external analog settings. The output voltage of
each DAC can be independently set and has a range of 0 V up to the supply voltage, with an 8-bit resolution.
When the user DACs are not used in a camera system, they can be put in the standby mode by programming
control bits in the control register.
internal timing
The SR and SV signals are required to operate the CDS, as previously explained. The user needs to
synchronize the SR and SV clocks with the CCD signal waveform. The output of the ADC is read out to external
circuitry by the ADCCLK signal, which is also used internally to control both ADC and PGA operations. It is
required that the positive half cycle of the ADCCLK signal always falls in between two adjacent SV pulses as
shown in Fig. 1. The user can then fine tune the ADCCLK timing in relation to the CDS timing to achieve optimal
performance.
The CLCCD
signal is used to activate the input clamping and the OBCLP signal is used to activate auto-optical
black and offset correction.
input blanking function
Large input transients may occur at the TLV990-40’s input during some period of operation which can saturate
the input circuits and cause long recovery time. To prevent circuit saturation the TLV990-40 includes an input
blanking function that blocks the input signals by disabling the CDS operation whenever the BLKG input is pulled
low. The TLV990-40 digital output will be set by the blanking data register after BLKG is pulled low.
NOTE:
If the BLKG pulse is located before the OBCLP pulse, there must be at least 4 pixels between the
rising edge of the BLKG pulse and the falling edge of the OBCLP pulse. If the BLKG pulse is located
after the OBCLP, the minimum number of pixels between the falling edge of the OBCLP and the
falling edge of the BLKG pulse should be equal to the number of optical black pixels per line + 4.
3-wire serial interface
A simple 3-wire (SCLK, SDIN, and CS) serial interface is provided to allow writing to the TLV990-40 internal
registers. Serial clock SCLK can be run at a maximum frequency of 40 MHz. Serial data SDIN is 16 bits long.
The two leading null bits are followed by four address bits for which the internal register is to be updated, and
then ten bits of data to be written to the register. The CS
pin must be held low to enable the serial port. Data
transfer is initiated by the incoming SCLK after CS
falls.
The SCLK polarity is selectable by pulling the SCKP pin either high or low.