Datasheet

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      
SLAS326A − JANUARY 2001 − REVISED MARCH 2004
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
REGISTER DEFINITION
blanking data register format
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 BDTA 0 0 0 0 0
blanking data register description
BIT NAME DESCRIPTION
D5 BDTA This register value appears at the digital output when BLKG is low. When this bit is set to 1, digital output during blanking
will be VB. Register default value = 0.
Default = 0000000000
ADCCLK internal delay register format
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X X X X X X ADL3 ADL2 ADL1 ADL0
ADCCLK internal delay register description
BIT NAME DESCRIPTION
D9−D4 X Reserved
D3−D0 ADL3−ADL0 These four bits set the internal ADCCLK delay.
ADL3 ADL2 ADL1 ADL0 Typical internal delay
0 0 0 0 0 ns (default)
:
:
1 1 1 1 10 ns
Default register value = XXXXXX0000
SR and SV internal delay register format
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X X SVL3 SVL2 SVL1 SVL0 SRL3 SRL2 SRL1 SRL0
SR and SV internal delay register description
BIT NAME DESCRIPTION
D9−D8 X Reserved
D7−D4 SVL3−SVL0 These four bits set the internal SV delay.
SVL3 SVL2 SVL1 SVL0 Typical internal delay
0 0 0 0 0 ns (default)
:
:
1 1 1 1 10 ns
D3−D0 SRL3−SRL0 These four bits set the internal SR delay.
SRL3 SRL2 SRL1 SRL0 Typical internal delay
0 0 0 0 0 ns (default)
:
:
1 1 1 1 10 ns
Default register value = XX00000000