Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 10 Bit TQFP 48



      

SLAS326A − JANUARY 2001 − REVISED MARCH 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

D Single-Chip CCD Analog Front-End

D 10-Bit, 40-MSPS

†

, A/D-Converter Single 3-V

Supply Operation

D Very Low Power: 200 mW Typical, 2-mW

Power-Down Mode

D Differential Nonlinearity Error:

< ±0.6 LSB Typical

D Integral Nonlinearity Error: < ±1.75 LSB

Typical

D Programmable Gain Amplifier (PGA) With

0-dB to 36-dB Gain Range (0.045 dB/Step)

D Automatic or Programmable Optical Black

Level and Offset Calibration With Digital

Filter and Bad Pixel Limits

D Additional DACs for External Analog

Setting

D Serial Interface for Register Configuration

D Internal-Reference Voltages

D 48-Pin TQFP Package

application

D Digital Still Camera

D Video Camcorder

description

The TLV990-40 is a complete CCD and video

signal processor/digitizer designed for digital still

camera and video camcorder applications.

The TLV990-40 performs all the analog-processing functions necessary to maximize the dynamic range,

corrects various errors associated with the CCD sensor, and then digitizes the results with an on-chip

high-speed analog-to-digital converter (ADC).

The key components of the TLV990-40 include: an input clamp circuit for CCD and analog video signals, a

correlated double sampler (CDS), a programmable-gain amplifier (PGA) with 0 to 36-dB gain range, two internal

digital-to-analog converters (DAC) for automatic or programmable optical black level and offset calibration, a

10-bit, 40-MSPS pipeline ADC, a parallel data port for easy microprocessor interface, a serial port for

configuring internal control registers, two additional DACs for external system control, and internal reference

voltages.

Designed in advanced CMOS process, the TLV990-40 operates from a single 3-V power supply with a normal

power consumption of 200 mW at 40 MSPS, and 2 mW in power-down mode.

Its very high throughput rate, single 3-V operation, very low-power consumption, and fully-integrated analog

processing circuitry make the TLV990-40 an ideal CCD and video signal-processing solution for electronic

video-camcorder applications.

This device is available in a 48-pin TQFP package and is specified over a –20°C to 75°C operating-temperature

range.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCKP

DACO2

DACO1

AGND3

DD3

DIGND

DIV

AGND5

RBD

RMD

RPD

DD5

DD1

AGND1

CLCCD

CLREF

567 8

RESET

SDIN

SCLK

35 34 33 32 3136 30

BLKG

AGND4

DD2

28 27 2629

10 11 12

ADCCLK

OBCLP

STBY

CCDIN

AGND2

PFB PACKAGE

(TOP VIEW)

DGND

DD4

TLV990-40PFB

†

The test register must be set to 1011 for 40 MSPS operation.

Summary of content (24 pages)

PAGE 1
SLAS326A − JANUARY 2001 − REVISED MARCH 2004 features application D Single-Chip CCD Analog Front-End D 10-Bit, 40-MSPS†, A/D-Converter Single 3-V D D D D D D D 48-Pin TQFP Package STBY RESET CS SDIN SCLK ADCCLK D PFB PACKAGE (TOP VIEW) BLKG CP CP AVDD4 AGND4 OBCLP D Supply Operation Very Low Power: 200 mW Typical, 2-mW Power-Down Mode Differential Nonlinearity Error: < ±0.6 LSB Typical Integral Nonlinearity Error: < ±1.
PAGE 2
SLAS326A − JANUARY 2001 − REVISED MARCH 2004 AVAILABLE OPTIONS PACKAGE DEVICE TA TQFP (PFB) −20°C to 75°C TLV990-40PFB functional block diagram AVDD1−5 CLCCD CLREF RPD RBD DVDD RMD DIVDD OE INT. REF. Clamp 1.
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SLAS326A − JANUARY 2001 − REVISED MARCH 2004 Terminal Functions TERMINAL NAME I/O DESCRIPTION NO.
PAGE 4
SLAS326A − JANUARY 2001 − REVISED MARCH 2004 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, AVDD, DVDD, DIVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD+0.3 V Digital input voltage range . .
PAGE 5
SLAS326A − JANUARY 2001 − REVISED MARCH 2004 electrical characteristics over recommended operating free-air temperature range, TA = 25°C, AVDD=DVDD=3 V, ADCCLK=40 MHz (unless otherwise noted) total device PARAMETER TEST CONDITIONS MIN AVDD operating current DVDD operating current Device power consumption Power consumption in power-down mode INL Full channel integral nonlinearity AVDD=DVDD= 2.7 V – 3.
PAGE 6
SLAS326A − JANUARY 2001 − REVISED MARCH 2004 electrical characteristics over recommended operating free-air temperature range, TA = 25°C, AVDD=DVDD=3 V, ADCCLK=40 MHz (unless otherwise noted) user digital-to-analog converters (DAC) PARAMETER TEST CONDITIONS MIN DAC resolution INL Integral nonlinearity DNL Differential nonlinearity MAX 8 Bits LSB 0 10 pF external load, settle to 1 mV UNIT ±0.75 ±0.
PAGE 7
SLAS326A − JANUARY 2001 − REVISED MARCH 2004 10 BIT-PGA GAIN CURVE 40 35 Gain − dB 30 25 20 15 10 5 0 0 200 400 600 800 PGA Codes 1000 1200 Figure 1 TYPICAL CHARACTERISTICS Optical Black Interval Dummy Black (Blanking) Interval Signal Interval CCD Output n n+1 SR tSRW SV tSvW BLKG CLCCD OBCLP ADCCLK Latency: 6 ADC Cycles tOD ADC OUT n Figure 2.
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SLAS326A − JANUARY 2001 − REVISED MARCH 2004 TYPICAL CHARACTERISTICS tCSF tCSR CS 1 2 3 4 5 6 DI15 DI14 DI13 DI12 DI11 DI10 7 16 SCLK SDIN DI9 DI0 SCKP Pin Is Pulled Low tCSF tCSR CS 1 2 3 4 5 6 DI15 DI14 DI13 DI12 DI11 DI10 7 16 SCLK SDIN SCKP Pin Is Pulled High Figure 3.
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SLAS326A − JANUARY 2001 − REVISED MARCH 2004 TYPICAL CHARACTERISTICS tSRD CCD IN tSVD SR SV tADC_SV ADCCLK MIN TIMING PARAMETER TYP MAX EXPLANATION tSRD Delay between sample reset (SR) rising edge and actual sampling instant (ns) 6 This is the fixed internal delay in the chip. The reset value of the CCD waveform should be stable until the end of this period.
PAGE 10
SLAS326A − JANUARY 2001 − REVISED MARCH 2004 APPLICATION INFORMATION AVDD 0.1 µF 1 µF AVDD 0.1 µF 0.1 µF 1 µF 1 µF 0.1 µF Inputs 1 µF 1 µF 9 10 RBD AGND5 RPD RMD AVDD1 V SS AVDD5 SV TLV990-40PFB D1 D2 D3 D4 D5 D6 11 12 35 Input 34 33 Inputs OE 8 DVDD D0 36 AVDD4 32 AGND4 31 OBCLP 30 STBY 29 RESET 28 CS 27 SDIN 26 SCLK 25 ADCCLK DGND SCKP 0.1 µF CP AGND3 DACO1 DACO2 6 7 DVDD 0.
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SLAS326A − JANUARY 2001 − REVISED MARCH 2004 REGISTER DEFINITION serial input data format DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 X X A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 0 0 0 0 Control register1 D9−D0 0 0 0 1 PGA gain register 0 0 1 0 User DAC1 register 0 0 1 1 User DAC2 register 0 1 0 0 Coarse offset DAC 0 1 0 1 Fine offset DAC 0 1 1 0
PAGE 12
SLAS326A − JANUARY 2001 − REVISED MARCH 2004 REGISTER DEFINITION PGA register format D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default PGA gain = 0000000000 or 0 dB user DAC1 and DAC2 registers format D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default user DAC register value = XX00000000 coarse offset DAC register format D9 D8
PAGE 13
SLAS326A − JANUARY 2001 − REVISED MARCH 2004 REGISTER DEFINITION optical black setup register format D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 OMUX1 OMUX0 HYS X SOFW1 SOFW0 MP PN2 PN1 PN0 optical black setup register description BIT NAME D8, D9 OMUX1, OMUX0 D7 HYS D6 X D5, D4 SOFW1, SOFW0 D3 MP DESCRIPTION These two bits multiplex digital output (data presented at D[9:0] pins): OMUX1 OMUX0 0 0 D[9:0] = ADC output (default) 0 1 D[9:0]
PAGE 14
SLAS326A − JANUARY 2001 − REVISED MARCH 2004 REGISTER DEFINITION hot/cold pixel limit register format D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X HFIT hot/cold pixel limit register description Bit Name D9 − D1 X D0 HFIT Description Reserved Set hot/cold pixel filter 0 − Apply Vb ± .
PAGE 15
SLAS326A − JANUARY 2001 − REVISED MARCH 2004 REGISTER DEFINITION blanking data register format D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 BDTA 0 0 0 0 0 blanking data register description BIT NAME D5 BDTA DESCRIPTION This register value appears at the digital output when BLKG is low. When this bit is set to 1, digital output during blanking will be VB. Register default value = 0.
PAGE 16
SLAS326A − JANUARY 2001 − REVISED MARCH 2004 REGISTER DEFINITION test register format D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TB9 TB8 TB7 TB6 X X TB3 TB2 X X Default register value =0110000000 These bits must be set to 1011 for 40 MSPS test register description BIT NAME DESCRIPTION D9−D6 TB9−TB6 These four bits are used to program internal DC bias current.
PAGE 17
SLAS326A − JANUARY 2001 − REVISED MARCH 2004 PRINCIPLES OF OPERATION ADC The ADC employs a pipelined architecture to achieve high throughput and low power consumption. Fullydifferential implementation and digital-error correction ensure 10-bit resolution. The latency of the ADC data output is 6 ADCCLK cycles, as shown in Figure 1. Pulling the OE pin (pin 24) high puts the ADC output in high impedance.
PAGE 18
SLAS326A − JANUARY 2001 − REVISED MARCH 2004 PRINCIPLES OF OPERATION device reset When pin RESET (pin 29) is pulled low, all internal registers are set to their default values. The device also resets itself when it is first powered on. In addition, the TLV990-40 has a software-reset function that resets the device when writing a control bit to the control register. See the register definition section for the register default values.
PAGE 19
SLAS326A − JANUARY 2001 − REVISED MARCH 2004 PRINCIPLES OF OPERATION automatic optical black and offset correction In the TLV990-40, the optical black and system channel-offset corrections are performed by an autodigital feedback loop. Two DACs are used to compensate for both channel offset and optical black offset. A coarse correction DAC (CDAC) is located before PGA gain stage, and a fine correction DAC (FDAC) is located after the gain stage.
PAGE 20
SLAS326A − JANUARY 2001 − REVISED MARCH 2004 PRINCIPLES OF OPERATION automatic optical black and offset correction (continued) Due to different exposure times, there might be a sudden optical black level shift at the start of each frame. Thus, a quick optical black level correction is desirable.
PAGE 21
PACKAGE OPTION ADDENDUM www.ti.com 3-Jul-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLV990-40PFB NRND TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV990-40PFBG4 NRND TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 22
MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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