Datasheet

t
d
= 211mst
d
= 211ms
Board Layout www.ti.com
Table 1. Threshold voltage, V
IT
, Values for Each TLV8xxxEVM
V
IT
(1)
Part
Min (V) Typ (V) Max (V)
TLV809K 2.87 2.93 2.99
TLV810S 2.87 2.93 2.99
TLV803S 2.87 2.93 2.99
(1)
V
IT
values taken from datasheet.
4.2 Timing
The TLV8xxx parts have a reset generator with a fixed delay time. An internal timer delays the return of
the output to the inactive state (high) to ensure proper system reset. The delay time (t
d(typ)
= 200ms) starts
after V
DD
has risen above the threshold voltage, V
IT
. When the supply voltage, V
DD
, drops below the V
IT
voltage, the output becomes active (low) again. Min and max values for t
d
can be found in the datasheet,
labeled Switching Characteristics.
Figure 3. Timing Diagram for TLV8xxxEVM
5 Board Layout
This section provides the TLV8xxxEVM board layout and illustrations.
5.1 Layout
NOTE: Board layouts are not to scale. These figures are intended to show how the board is laid out; they
are not intended to be used for manufacturing TLV8xxx EVM PCBs.
4
TLV8xxxEVM-019 Evaluation Modules SLVU461– May 2011
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