Datasheet

OFF
ON
GND
EN
GND
VIN Vout
J1 J3
J2
J4
JP1
C1
1.0 Fm
C2
1.0 Fm
4
IN
3
EN
5
PWPD
2
GND
1
OUT
U1
TLV717xxPDQN
Schematic and Bill of Materials www.ti.com
Figure 5. Bottom-Layer Routing
7 Schematic and Bill of Materials
7.1 Schematic
Figure 6. TLV71733PEVM-072 Schematic
7.2 Bill of Materials
Table 1. TLV71733PEVM-072 Bill of Materials
Count RefDes Value Description Size Part Number MFR
2 C1, C2 1.0µF Capacitor, Ceramic, Low Inductance, 10V, [X7R], [10%] 0603 STD STD
4 J1-4 PTC36SAAN Header, 2-pin, 100mil spacing 0.100 inch x 2 PEC36SAAN Sullins
1 JP1 Header, 3-pin, 100mil spacing 0.100 inch x 3 Sullins
1 U1 TLV71733PDQN IC, 200mA, Low IQ, LDO Regulator for Portables uDFN TLV71733PDQN TI
1 — PCB, 1 In x 1 In x 1 In PWR072 Any
6
TLV71733PEVM-072 Evaluation Module SLVU553–October 2011
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