Datasheet

Board Layout
www.ti.com
Table 1. Thermal Resistance, q_ja , and Maximum Power Dissipation
Maximum Dissipation Maximum Dissipation
Board Package q_ja Without Derating Without Derating
(T
A
= 25°C) (T
A
= 70d°C)
High-K DSE 206°C/W 485 mW 269 mW
TPS710xxEVM-595 DSE 120°C/W 833 mW 458 mW
The thermal resistance for the TPS710xxEVM-595, q_ja, is the measured value for this particular layout
scheme. The maximum power dissipation is proportional to the volume of copper volume connected to the
package.
6 Board Layout
Figure 4. Assembly Layer
6
TLV7101828EVM-595 SLVU404September 2010
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated