Datasheet
T = T + P
J A D JA
q?
Thermal Guidelines and Layout Recommendations
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5 Thermal Guidelines and Layout Recommendations
Thermal management is a key design component of any power converter, and is especially important
when the power dissipation in the LDO is high. Use Equation 1 to approximate the maximum power
dissipation for the particular ambient temperature.
Where:
T
J
= junction temperature
T
A
= ambient temperature
P
D
= power dissipation in the IC (in watts)
θ
JA
= thermal resistance from junction to ambient (1)
All temperatures are in degrees Celsius (°C).
The maximum silicon junction temperature, T
J
, must not be allowed to exceed +150°C. The layout design
must use copper trace and plane areas effectively as thermal sinks, in order not to allow T
J
to exceed the
absolute maximum ratings under all temperature conditions and voltage conditions across the application.
Designers should carefully consider the thermal design of the PCB for optimal performance over
temperature. For this EVM, Figure 4 shows that the PCB top ground plane has six, 6-mil (0,1524-mm)
thermal via connections to the bottom side copper ground plane to dissipate heat. The PCB is a two-layer
board with 2-oz copper on top and bottom layers. The YFF package drawing can be found at the Texas
Instruments web site in the TLV70528 LDO product folder.
Table 1 shows the Dissipation Ratings table of the TLV70528 data sheet for comparison with the thermal
resistance, θ
JA
, calculated for this EVM layout to show the wide variation in thermal resistances for given
copper areas. The High-K value is determined using a standard JEDEC High-K (2s2p) board having
dimensions of 3-inch x 3-inch with 1-ounce internal power and ground planes and 2-ounce copper traces
on top and bottom of the board.
Table 1. Thermal Resistance (θ
JA
) and Maximum Power Dissipation
Max Dissipation Max Dissipation
without Derating without Derating
Board Package θ
JA
(T
A
= +25°C) (T
A
= +70°C)
High-K YFF 268°C/W 370 mW 205 mW
TLV70528EVM YFF 107°C/W 1.16 W 747 mW
The thermal resistance for the TLV705xxxEVM-596, θ
JA
, is the measured value for this particular layout
scheme. The maximum power dissipation is proportional to the volume of copper volume connected to the
package.
4
TLV705xxxEVM-596 Evaluation Module SLVU439–August 2011
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