Datasheet

P
D
+
ǒ
V
IN
* V
OUT
Ǔ
I
OUT
P
D(max)
+
T
J
max * T
A
R
qJA
TLV704xx
www.ti.com SBVS148C –OCTOBER 2010– REVISED AUGUST 2011
APPLICATION INFORMATION
The TLV704xx series belong to a family of ultralow I
Q
T
A
is the ambient temperature.
LDO regulators. I
Q
remains fairly constant over the
The regulator dissipation is calculated using
complete output load current and temperature range.
Equation 2:
The devices are ensured to operate over a
temperature range of –40°C to +125°C.
(2)
Power dissipation resulting from quiescent current is
INPUT AND OUTPUT CAPACITOR
negligible.
REQUIREMENTS
The TLV704 requires a 1-µF or larger capacitor
REGULATOR PROTECTION
connected between OUT and GND for stability.
Ceramic or tantalum capacitors can be used. Larger The TLV704xx series of LDO regulators use a
value capacitors result in better transient and noise PMOS-pass transistor that has a built-in back diode
performance. that conducts reverse current when the input voltage
drops below the output voltage (for example, during
Although an input capacitor is not required for
power-down). Current is conducted from the output to
stability, when a 0.1-µF or larger capacitor is placed
the input and is not internally limited. If extended
between IN and GND, it counteracts reactive input
reverse voltage operation is anticipated, external
sources and improves transient and noise
limiting might be appropriate.
performance. Higher value capacitors are necessary
if large, fast rise time load transients are anticipated. The TLV704xx features internal current limiting.
During normal operation, the TLV704xx limits output
current to approximately 250 mA. When current
BOARD LAYOUT RECOMMENDATIONS
limiting engages, the output voltage scales back
Input and output capacitors should be placed as
linearly until the overcurrent condition ends. Take
close to the device pins as possible. To avoid
care not to exceed the rated maximum operating
interference of noise and ripple on the board, it is
junction temperature of +125°C. Continuously running
recommended that the board be designed with
the device under conditions where the junction
separate ground planes for V
IN
and V
OUT
, with the
temperature exceeds +125°C degrades device
ground plane connected only at the device GND pin.
reliability.
In addition, the ground connection for the output
The ability to remove heat from the die is different for
capacitor should be connected directly to the device
each package type, presenting different
GND pin.
considerations in the printed circuit board (PCB)
layout. The PCB area around the device that is free
POWER DISSIPATION AND JUNCTION
of other components moves the heat from the device
TEMPERATURE
to the ambient air. Performance data for JEDEC
To ensure reliable operation, worst-case junction
high-K boards are given in the Power Dissipation
temperature should not exceed +125°C. This
Rating table. Using heavier copper increases the
restriction limits the power dissipation the regulator
effectiveness in removing heat from the device. The
can handle in any given application. To ensure the
addition of plated through-holes to heat-dissipating
junction temperature is within acceptable limits,
layers also improves heatsink effectiveness. Power
calculate the maximum allowable dissipation, P
D(max)
,
dissipation depends on input voltage and load
and the actual dissipation, P
D
, which must be less
conditions. Power dissipation (P
D
) is equal to the
than or equal to P
D(max)
.
product of the output current and the voltage drop
across the output pass element, as shown in
The maximum power dissipation limit is determined
Equation 2.
using Equation 1:
PACKAGE MOUNTING
(1)
Solder pad footprint recommendations for the
TLV704xx are available from the Texas Instruments
where:
web site at www.ti.com through the TLV704 series
T
J
max is the maximum allowable junction
product folders. The recommended land pattern for
temperature.
the DBV package is appended to this data sheet.
R
θJA
is the thermal resistance junction-to-ambient
for the package (see the Power Dissipation
Rating table).
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