Datasheet

TLV70012A-Q1, TLV70025-Q1, TLV70028-Q1
TLV70030-Q1, TLV70032-Q1, TLV70033-Q1
www.ti.com
SLVSA61F FEBRUARY 2010REVISED AUGUST 2013
APPLICATION INFORMATION
The TLV700xx-Q1 belongs to a new family of next-generation value LDO regulators. It consumes low quiescent
current and delivers excellent line and load transient performance. These characteristics, combined with low
noise, very good PSRR with little (V
IN
V
OUT
) headroom, make this device ideal for RF portable applications.
This family of regulators offers subband-gap output voltages down to 0.7 V, current limit, and thermal protection,
and is specified from –40°C to 125°C.
Input and Output Capacitor Requirements
1.0-μF X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal
variation in value and equivalent series resistance (ESR) over temperature.
However, the TLV700xx-Q1 is designed to be stable with an effective capacitance of 0.1 μF or larger at the
output. Thus, the device is stable with capacitors of other dielectric types as well, as long as the effective
capacitance under operating bias voltage and temperature is greater than 0.1 μF. This effective capacitance
refers to the capacitance that the LDO sees under operating bias voltage and temperature conditions; that is, the
capacitance after taking both bias voltage and temperature derating into consideration. In addition to allowing the
use of cheaper dielectrics, this capability of being stable with 0.1-μF effective capacitance also enables the use
of smaller-footprint capacitors that have higher derating in size- and space-constrained applications.
Note that using a 0.1-μF rated capacitor at the output of the LDO does not ensure stability because the effective
capacitance under the specified operating conditions would be less than 0.1 μF. Maximum ESR should be less
than 200 mΩ.
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1-
μF, low-ESR capacitor across the IN pin and GND in of the regulator. This capacitor counteracts reactive input
sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be
necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power
source. If source impedance is more than 2 Ω, a 0.1-μF input capacitor may be necessary to ensure stability.
Board Layout Recommendations to Improve PSRR and Noise Performance
Input and output capacitors should be placed as close to the device pins as possible. To improve ac performance
such as PSRR, output noise, and transient response, it is recommended that the board be designed with
separate ground planes for V
IN
and V
OUT
, with the ground plane connected only at the GND pin of the device. In
addition, the ground connection for the output capacitor should be connected directly to the GND pin of the
device. High-ESR capacitors may degrade PSRR performance.
Internal Current Limit
The TLV700xx-Q1 internal current limit helps to protect the regulator during fault conditions. During current limit,
the output sources a fixed amount of current that is largely independent of the output voltage. In such a case, the
output voltage is not regulated, and is V
OUT
= I
LIMIT
× R
LOAD
. The PMOS pass transistor dissipates (V
IN
V
OUT
) ×
I
LIMIT
until thermal shutdown is triggered and the device turns off. As the device cools down, it is turned on by the
internal thermal-shutdown circuit. If the fault condition continues, the device cycles between current limit and
thermal shutdown. See the Thermal Information section for more details.
The PMOS pass element in the TLV700xx-Q1 has a built-in body diode that conducts current when the voltage
at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is
anticipated, external limiting to 5% of the rated output current is recommended.
Shutdown
The enable pin (EN) is active-high and is compatible with standard and low-voltage TTL-CMOS levels. When
shutdown capability is not required, EN can be connected to the IN pin.
Dropout Voltage
The TLV700xx-Q1 uses a PMOS pass transistor to achieve low dropout. When (V
IN
V
OUT
) is less than the
dropout voltage (V
DO
), the PMOS pass device is in the linear region of operation and the input-to-output
resistance is the r
DS(on)
of the PMOS pass element. V
DO
scales approximately with output current because the
PMOS device behaves as a resistor in dropout.
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