Datasheet

TLV62065
SLVSAC4A –NOVEMBER 2010–REVISED JULY 2012 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PART MAXIMUM OUTPUT PACKAGE PACKAGE
T
A
OUTPUT VOLTAGE ORDERING
(2)
NUMBER CURRENT DESIGNATOR MARKING
–40°C to TLV62065 Adjustable 2.0 A DSG TLV62065DSG QVB
85°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) The DSG (SON-8) packages is available in tape on reel. Add R suffix to order quantities of 3000 parts per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
MIN MAX
Voltage Range
(2)
AVIN, PVIN –0.3 7
EN, MODE, FB –0.3 to V
IN
+0.3 < 7 V
SW –0.3 7
Current (source) Peak output Internally limited A
Electrostatic Discharge (HBM) QSS 009-105 (JESD22-A114A)
(3)
2
kV
Electrostatic Discharge (CDM) QSS 009-147 (JESD22-C101B.01) 1
Electrostatic Discharge (Machine model) 200 V
T
J
–40 125 °C
Temperature
T
stg
–65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
THERMAL INFORMATION
TLV62065
THERMAL METRIC
(1)
DSG UNITS
8 PINS
θ
JA
Junction-to-ambient thermal resistance 65.2
θ
JC(top)
Junction-to-case(top) thermal resistance 93.3
θ
JB
Junction-to-board thermal resistance 30.1
°C/W
ψ
JT
Junction-to-top characterization parameter 0.5
ψ
JB
Junction-to-board characterization parameter 47.4
θ
JC(bottom)
Junction-to-case(bottom) thermal resistance 7.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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