Datasheet

TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• 9
internal clock
With CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART, and conversion begins at the rising
edge of CSTART. The internal clock turns on at the rising edge of CSTART. The internal clock is disabled after each conversion.
OR
Auto Powerdown
CS
WR
CSTART
INTCLK
RD
D[0:7]
INT
EOC
Config
Data
ADC
Data
ADC
Data
t
su(CSL_WRL)
t
h(WRH_CSH)
t
d(CSH_CSTARTL)
t
(sample)
t
su(DAV_WRH)
t
h(WRH_DAV)
t
c
t
su(CSL_RDL)
t
h(RDH_CSH)
t
en(RDL_DAV)
t
dis(RDH_DAV)
t
c
t
su(CSL_RDL)
t
en(RDL_DAV)
t
(STARTOSC)
t
(STARTOSC)
9
10
10
Auto Powerdown
Figure 5. Input Conversion – Hardware CSTART, Internal Clock