Datasheet

TLV571 2.7 V to 5.5 V, 1-CHANNEL, 8-BIT RARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
start of conversion mechanism (continued)
CLK
D[0:7]
EOC
t
su(CSL_WRL)
t
h(WRH_CSH)
t
d(CSH_CSTARTL)
t
(sample)
t
su(DAV_WRH)
t
h(WRH_DAV)
t
c
(10 CLKs)
t
en(RDL_DAV)
t
dis(RDH_DAV)
t
c
t
su(CSL_RDL)
t
en(RDL_DAV)
OR
Auto Powerdown
ADC ADC
Config
Data
t
(sample)
su(CSL_RDL)
t
h(RDH_CSH)
t
CS
WR
CSTART
RD
INT
Figure 4. Input Conversion – Hardware CSTART, External Clock