Datasheet

TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
control registers
0:
Binary
1:
2’s
Complement
0:
Reserved
Bit,
Always
Write 0
0:
INT. OSC.
SLOW
1:
INT. OSC.
FAST
STARTSEL
A1 A0 D4 D3 D2 D1 D0D5
Control Register Zero (CR0)
D4D5 D3 D2 D1 D0
PROGEOC
CLKSEL SWPWDN Don’t Care
0:
HARDWARE
START
(CSTART)
A(1:0)=00
1:
SOFTWARE
START
0:
INT
1:
EOC
0:
Internal
Clock
1:
External
Clock
0:
NORMAL
1:
Powerdown
Reserved
Control Register One (CR1)
D4D5 D1 D0
OSCSPD 0 Reserved 0 Reserved OUTCODE Reserved
0:
Reserved
Bit
Always
Write 0
A(1:0)=01
0:
Reserved
Bit
Always
Write 0
D3 D2
Don’t Care
Don’t Care
Don’t Care
0:
Reserved
Bit,
Always
Write 0
Figure 2. Input Data Format
hardware configuration option
The TLV571 can configure itself. This option is enabled when the WR
pin is tied to ground and a dummy RD
signal is applied. The ADC is now fully configured. Zeros or default values are applied to both control registers.
The ADC is configured ideally for 3-V operation, which means the internal OSC is set at 10 MHz and hardware
start of conversion using CSTART.
ADC conversion modes
The TLV571 provides two start of conversion modes. Table 1 explains these modes in more detail.