Datasheet

TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements, AV
DD
= DV
DD
= 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
c(CLK)
In
p
ut clock Cycle time
DV
DD
= 4.5 V to 5.5 V 50 ns
t
c
(CLK)
In ut
clock
Cycle
time
DV
DD
= 2.7 V to 3.3 V 100 ns
t
(sample)
Reset and sampling time 6
SYSCLK
Cycles
t
c
Total conversion time 10
SYSCLK
Cycles
t
wL(EOC)
Pulse width, end of conversion, EOC 10
SYSCLK
Cycles
t
wL(INT)
Pulse width, interrupt 1
SYSCLK
Cycles
t
(STARTOSC)
Start-up time, internal oscillator 100 ns
t
d(CSH_CSTARTL)
Delay time, CS high to CSTART low 10 ns
t
en(RDL DAV)
Enable time data out
DV
DD
= 5 V at 50 pF 20 ns
t
en
(RDL
_
DAV)
Enable
time
,
data
out
DV
DD
= 3 V at 50 pF 40 ns
t
dis(RDH DAV)
Disable time data out
DV
DD
= 5 V at 50 pF 5 ns
t
di
s
(RDH
_
DAV)
Disable
time
,
data
out
DV
DD
= 3 V at 50 pF 10 ns
t
su(CSL_WRL)
Setup time, CS to WR 5 ns
t
h(WRH_CSH)
Hold time, CS to WR 5 ns
t
w(WR)
Pulse width, write 1
Clock
Period
t
w(RD)
Pulse width, read 1
Clock
Period
t
su(DAV_WRH)
Setup time, data valid to WR 10 ns
t
h(WRH_DAV)
Hold time, data valid to WR 5 ns
t
su(CSL_RDL)
Setup time, CS to RD 5 ns
t
h(RDH_CSH)
Hold time, CS to RD 5 ns
t
h(WRL_EXTXLKH)
Hold time WR to clock high 5 ns
t
h(RDL_EXTCLKH)
Hold time RD to clock high 5 ns
t
h(CSTARTL_EXTCLKH)
Hold time CSTART to clock high 5 ns
t
su(WRH_EXTCLKH)
Setup time WR high to clock high 5 ns
t
su(RDH_EXTCLKH)
Setup time RD high to clock high 5 ns
t
su(CSTARTH_EXTCLKH)
Setup time CSTART high to clock high 5 ns
t
d(EXTCLK_CSTARTL)
Delay time clock low to CSTART low 5 ns
NOTE: Specifications subject to change without notice.
Data valid is denoted as DAV.