Datasheet

TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
simplified analog input analysis
Using the equivalent circuit in Figure 10, the time required to charge the analog input capacitance from 0 to V
S
within 1/2 LSB, t
ch
(1/2 LSB), can be derived as follows.
The capacitance charging voltage is given by:
Where
R
t
= R
s
+ R
i
R
i
= R
i(ADC)
t
ch
= Charge time
V
C(t)
V
S
1–e
–t
ch
R
t
C
i
The input impedance R
i
is 718 Ω at 5 V, and is higher (~ 1.25 kΩ) at 2.7 V. The final voltage to 1/2 LSB is given
by:
V
C
(1/2 LSB) = V
S
– (V
S
/512)
Equating equation 1 to equation 2 and solving for cycle time t
c
gives:
and time to change to 1/2 LSB (minimum sampling time) is:
t
ch
(1/2 LSB) = R
t
× C
i
× ln(512)
V
S
V
S
512 V
S
1–e
–t
ch
R
t
C
i
Where
ln(512) = 6.238
Therefore, with the values given, the time for the analog input signal to settle is:
t
ch
(1/2 LSB) = (R
s
+ 718 Ω) × 15 pF × ln(512)
This time must be less than the converter sample time shown in the timing diagrams. Which is 6x SCLK.
t
ch
(1/2 LSB) ≤ 6x 1/f
(SCLK)
Therefore the maximum SCLK frequency is:
Max(f
(SCLK)
) = 6/t
ch
(1/2 LSB) = 6/(ln(512) × R
t
× C
i
)
(1)
(2)
(3)
(4)
(5)
(6)