Datasheet

TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
grounding and decoupling considerations
General practices should apply to the PCB design to limit high frequency transients and noise that are fed back
into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed.
In most cases 0.1-µF ceramic chip capacitors are adequate to keep the impedance low over a wide frequency
range. Since their effectiveness depends largely on the proximity to the individual supply pin, they should be
placed as close to the supply pins as possible.
To reduce high frequency and noise coupling, it is highly recommended that digital and analog grounds be
shorted immediately outside the package. This can be accomplished by running a low impedance line between
DGND and AGND under the package.
TLV571
100 nF
DGND
DV
DD
AV
DD
AGND
REFP
REFM
100 nF
100 nF
V
REFP
V
REFM
AV
DD
DV
DD
Figure 9. Placement for Decoupling Capacitors
power supply ground layout
Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the ADC AGND terminal to the system analog ground plane making sure that analog ground
currents are well managed.
R
s
V
S
V
C
15 pF
Driving Source
†
TLV571
C
i
V
I
V
I
= Input Voltage at AIN
V
S
= External Driving Source Voltage
R
s
= Source Resistance
R
i(ADC)
= Input Resistance of ADC
C
i
= Input Capacitance
V
C
= Capacitance Charging Voltage
†
Driving source requirements:
• Noise and distortion for the source must be equivalent to the resolution of the converter.
• R
s
must be real at the input frequency.
R
i(ADC)
AIN
Figure 10. Equivalent Input Circuit Including the Driving Source