Datasheet

TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• 11
software START conversion (continued)
internal clock
With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. Conversion begins 6 clocks after sampling
begins. The internal clock begins at the rising edge of WR. The internal clock is disabled after each conversion. Subsequent sampling begins
at the rising edge of RD.
OR
Auto Powerdown
ADC
CS
WR
RD
INTCLK
D[0:7]
INT
EOC
Config
Data
ADC
Data
t
su(CSL_WRL)
t
h(WRH_CSH)
t
(sample)
t
su(DAV_WRH)
t
h(WRH_DAV)
t
c
t
su(CSL_RDL)
t
h(RDH_CSH)
t
en(RDL_DAV)
t
dis(RDH_DAV)
t
c
t
(STARTOSC)
t
(STARTOSC)
t
(sample)
456 045015 15
Auto Powerdown
Figure 7. Input Conversion – Software Start, Internal Clock