Datasheet

www.ti.com
ELECTRICAL CHARACTAERISTICS (CONTINUED)
DIGITAL INPUT TIMING REQUIREMENTS
PARAMETER MEASUREMENT INFORMATION
t
wL
SCLK
CS
DIN
D15 D14 D13 D12 D1 D0 XX
1
X
2 3 4 5 15 16
X
t
wH
t
su(D)
t
h(D)
t
su(CS-CK)
t
su(C16-CS)
TLV5637
SLAS224C – JUNE 1999 – REVISED JUNE 2007
over recommended operating conditions (unless otherwise noted)
ANALOG OUTPUT DYNAMIC PERFORMANCE
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Fast 0.8 2.4
t
s(FS)
Output settling time, full scale R
L
= 10k Ω , C
L
= 100pF, See
(1)
µs
Slow 2.8 5.5
Fast 0.4 1.2
t
s(CC)
Output settling time, code to code R
L
= 10k Ω , C
L
= 100pF, See
(2)
µs
Slow 0.8 1.6
Fast 12
SR Slew rate R
L
= 10k Ω , C
L
= 100pF, See
(3)
V/µs
Slow 1.8
Glitch energy DIN = 0 to 1, f
CLK
= 100kHz, CS = V
DD
5 nV-S
SNR Signal-to-noise ratio 53 56
S/(N+D) Signal-to-noise + distortion 50 54
f
s
= 480kSPS, f
out
= 1kHz, R
L
= 10k Ω , C
L
= 100pF dB
THD Total harmonic distortion 61 50
SFDR Spurious free dynamic range 51 62
(1) Settling time is the time for the output signal to remain within ±0.5LSB of the final measured value for a digital input code change of
0x020 to 0xFDF or 0xFDF to 0x020 respectively. Not tested, assured by design.
(2) Settling time is the time for the output signal to remain within ± 0.5LSB of the final measured value for a digital input code change of one
count. Not tested, assured by design.
(3) Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
MIN NOM MAX UNIT
t
su(CS-CK)
Setup time, CS low before first negative SCLK edge 10 ns
t
su(C16-CS)
Setup time, 16
th
negative SCLK edge (when D0 is sampled) before CS rising edge 10 ns
t
wH
SCLK pulse width high 25 ns
t
wL
SCLK pulse width low 25 ns
t
su(D)
Setup time, data ready before SCLK falling edge 10 ns
t
h(D)
Hold time, data held valid after SCLK falling edge 5 ns
Figure 1. Timing Diagram
6
Submit Documentation Feedback