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DIGITAL INPUT TIMING REQUIREMENTS
PARAMETER MEASUREMENT INFORMATION
X Data X
X Address X
t
su(D)
t
su(A)
t
h(DA)
t
wH(WE)
t
su(WE-LD)
t
w(LD)
t
su(CS-WE)
D(0-7)
A(0,1)
CS
WE
LDAC
LSWX X MSW X
0X X 1 X
D(0-7)
A(0,1)
CS
WE
LDAC
TLV5633C
TLV5633I
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
MIN NOM MAX UNIT
t
su(CS-WE)
Setup time, CS low before negative WE edge 15 ns
t
su(D)
Setup time, data ready before positive WE edge 10 ns
t
su(A)
Setup time, addresses ready before positive WE edge 20 ns
t
h(DA)
Hold time, data and addresses held valid after positive WE edge 5 ns
t
su(WE-LD)
Setup time, positive WE edge before LDAC low 5 ns
t
wH(WE)
Pulse duration, WE high 20 ns
t
w(LD)
Pulse duration, LDAC low 23 ns
Figure 1. Timing Diagram
Figure 2. Example of a Complete Write Cycle (MSW, LSW) Using LDAC for Update
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