Datasheet

DIGITAL INPUT TIMING REQUIREMENTS
TLV5630
TLV5631
TLV5632
www.ti.com .................................................................................................................................................... SLAS269F – MAY 2000 – REVISED NOVEMBER 2008
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL OUTPUT
High-level digital output R
L
= 10 k Ω
V
OH
2.6 V
voltage
Low-level digital output R
L
= 10 k Ω
V
OL
0.4 V
voltage
Output voltage rise time R
L
= 10 k Ω , C
L
= 20 pF, Includes propagation delay 5 10 ns
ANALOG OUTPUT DYNAMIC PERFORMANCE
Fast 1 3
Output settling time, full
t
s(FS)
R
L
= 10 k Ω , C
L
= 100 pF, See
(5)
µ s
scale
Slow 3 7
Fast 0.5 1
Output settling time,
t
s(CC)
R
L
= 10 k Ω , C
L
= 100 pF, See
(6)
µ s
code to code
Slow 1 2
Fast 4 10
SR Slew rate R
L
= 10 k Ω , C
L
= 100 pF, See
(7)
V/ µ s
Slow 1 3
Glitch energy See
(8)
4 nV-s
Channel crosstalk 10 kHz sine, 4 V
PP
90 dB
(5) Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of
0x080 to 0xFFF and 0xFFF to 0x080, respectively. Assured by design; not tested.
(6) Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one
count. The max time applies to code changes near zero scale or full scale. Assured by design; not tested.
(7) Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
(8) Code transition: TLV5630 - 0x7FF to 0x800, TLV5631 - 0x7FCto 0x800, TLV5632 - 0x7F0 to 0x800.
PARAMETER MIN TYP MAX UNIT
t
su(FS-CK)
Setup time, FS low before next negative SCLK edge 8 ns
Setup time, 16
th
negative edge after FS low on which bit D0 is sampled before rising edge
t
su(C16-FS)
10 ns
of FS. µ C mode only
t
su(FS-C17)
µ C mode, setup time, FS high before 17
th
negative edge of SCLK. 10 ns
t
su(CK-FS)
DSP mode, setup time, SLCK low before FS low. 5 ns
t
wL(LDAC)
LDAC duration low 10 ns
t
wH
SCLK pulse duration high 16 ns
t
wL
SCLK pulse duration low 16 ns
t
su(FS-CK)
Setup time, FS low before first negative SCLK edge 8 ns
t
su(D)
Setup time, data ready before SCLK falling edge 8 ns
t
h(D)
Hold time, data held valid after SCLK falling edge 5 ns
t
wH(FS)
FS duration high 10 ns
t
wL(FS)
FS duration low 10 ns
See AC
t
s
Settling time
specs
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