Datasheet

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SLAS232A − JUNE1999 − REVISED JULY 2002
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
analog output dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SR
Output slew rate
C
L
= 100 pF, R
L
= 10 kΩ,
V
O
= 10% to 90%,
Fast 5 V/µs
SR Output slew rate
LL
V
O
= 10% to 90%,
V
ref
= 2.048 V, 1024 V
Slow 1 V/µs
t
s
Output settling time
To
±
0.1 LSB, C
L
= 100 pF,
Fast 2.5 4
s
t
s
Output settling time
To ± 0.1 LSB, C
L
= 100 pF,
R
L
= 10 kΩ, See Notes 12 and 14
Slow 8.5 18
µs
t
s(c)
Output settling time, code to code
To
±
0.1 LSB, C
L
= 100 pF,
Fast 1
s
t
s(c)
Output settling time, code to code
To ± 0.1 LSB, C
L
= 100 pF,
R
L
= 10 kΩ, See Notes 13 and 14
Slow 2
µs
Glitch energy Code transition from 7F0 to 800 10 nV-sec
SNR Signal-to-noise ratio
Sinewave generated by DAC,
57
S/(N+D) Signal to noise + distortion
Sinewave generated by DAC,
Reference voltage = 1.024 at 3 V and 2.048 at 5 V,
49
dB
THD Total harmonic distortion
Reference voltage = 1.024 at 3 V and 2.048 at 5 V,
f
s
= 400 KSPS, f
OUT
= 1.1 kHz sinewave,
C
L
= 100 pF, R
L
= 10 kΩ, BW = 20 kHz
−50
dB
SFDR Spurious free dynamic range
f
s
= 400 KSPS, f
OUT
= 1.1 kHz sinewave,
C
L
= 100 pF, R
L
= 10 kΩ, BW = 20 kHz
60
NOTES: 12. Settling time is the time for the output signal to remain within ± 0.1 LSB of the final measured value for a digital input code change
of 0x020 to 0xFF0 or 0xFF0 to 0x020.
13. Settling time is the time for the output signal to remain within ± 0.1 LSB of the final measured value for a digital input code change
of one count.
14. Limits are ensured by design and characterization, but are not production tested.
digital input timing requirements
MIN NOM MAX UNIT
t
su(CS−FS)
Setup time, CS low before FS↓ 10 ns
t
su(FS−CK)
Setup time, FS low before first negative SCLK edge 8 ns
t
su(C16−FS)
Setup time, sixteenth negative SCLK edge after FS low on which bit D0 is sampled before
rising edge of FS
10 ns
t
su(C16−CS)
Setup time. The first positive SCLK edge after D0 is sampled before CS rising edge. If FS
is used instead of the SCLK positive edge to update the DAC, then the setup time is between
the FS rising edge and CS rising edge.
10 ns
t
wH
Pulse duration, SCLK high 25 ns
t
wL
Pulse duration, SCLK low 25 ns
t
su(D)
Setup time, data ready before SCLK falling edge 8 ns
t
h(D)
Hold time, data held valid after SCLK falling edge 5 ns
t
wH(FS)
Pulse duration, FS high 20 ns