Datasheet

TLV5626
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A –JUNE 1999 – REVISED JUNE 2000
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
digital input timing requirements
MIN NOM MAX UNIT
t
su(CS–CK)
Setup time, CS low before first negative SCLK edge 10 ns
t
su(C16-CS)
Setup time, 16
th
negative SCLK edge (when D0 is sampled) before CS rising edge 10 ns
t
wH
SCLK pulse width high 25 ns
t
wL
SCLK pulse width low 25 ns
t
su(D)
Setup time, data ready before SCLK falling edge 10 ns
t
h(D)
Hold time, data held valid after SCLK falling edge 5 ns
PARAMETER MEASUREMENT INFORMATION
t
wL
SCLK
CS
DIN
D15 D14 D13 D12 D1 D0 XX
1
X
2 3 4 5 15 16
X
t
wH
t
su(D)
t
h(D)
t
su(CS-CK)
t
su(C16-CS)
Figure 1. Timing Diagram