Datasheet

TLV5626
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A –JUNE 1999 – REVISED JUNE 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
(Continued)
reference pin configured as output (REF)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
ref(OUTL)
Low reference voltage 1.003 1.024 1.045 V
V
ref(OUTH)
High reference voltage V
DD
> 4.75 V 2.027 2.048 2.069 V
I
ref(source)
Output source current 1 mA
I
ref(sink)
Output sink current –1 mA
Load capacitance 100 pF
PSRR Power supply rejection ratio –65 dB
reference pin configured as input (REF)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
I
Input voltage 0 V
DD–1.5
V
R
I
Input resistance 10 MΩ
C
I
Input capacitance 5 pF
Reference in
p
ut bandwidth
REF=02V +1024Vdc
Fast 1.3 MHz
Reference
inp
u
t
band
w
idth
REF
=
0
.
2
V
pp
+
1
.
024
V
dc
Slow 525 kHz
Reference feedthrough REF = 1 V
pp
at 1 kHz + 1.024 V dc (see Note 10) –80 dB
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
IH
High-level digital input current V
I
= V
DD
1 µA
I
IL
Low-level digital input current V
I
= 0 V –1 µA
C
i
Input capacitance 8 pF
analog output dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
(FS)
Out
p
ut settling time full scale
R
L
= 10 kΩ,C
L
= 100 pF,
Fast 0.8 2.4
µs
t
s(FS)
O
u
tp
u
t
settling
time
,
f
u
ll
scale
L
,
L
,
See Note 11
Slow 2.8 5.5
µ
s
t
(CC)
Out
p
ut settling time code to code
R
L
= 10 kΩ,C
L
= 100 pF,
Fast 0.4 1.2
µs
t
s(CC)
O
u
tp
u
t
settling
time
,
code
to
code
L
,
L
,
See Note 12
Slow 0.8 1.6
µ
s
SR
Slew rate
R
L
= 10 kΩ,C
L
= 100 pF,
Fast 12
V/µs
SR
Sle
w
rate
L
,
L
,
See Note 13
Slow 1.8
V/
µ
s
Glitch energy
DIN = 0 to 1, f
CLK
= 100 kHz,
CS
= V
DD
5 nV–S
SNR Signal-to-noise ratio 53 57
S/(N+D) Signal-to-noise + distortion
f
s
= 480 kSPS, f
out
= 1 kHz,
48 47
dB
THD Total harmonic distortion
s
,
out
,
R
L
= 10 kΩ,C
L
= 100 pF
–50 –48
dB
SFDR Spurious free dynamic range 50 62
NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0xFD0 or 0xFD0 to 0x020 respectively. Not tested, assured by design.
12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.