Datasheet


      
   
SLAS233D − JULY 1999 − REVISED JULY 2002
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Serial
Interface
and
Control
8-Bit
DAC B
Latch
SCLK
DIN
CS
OUTA
Power-On
Reset
x2
8
Power and
Speed Control
2
8-Bit
DAC A
Latch
8
REF AGND V
DD
8 8
OUTB
x2
Buffer
8
Terminal Functions
TERMINAL
I/O/P
DESCRIPTION
NAME NO.
I/O/P
DESCRIPTION
AGND 5 P Ground
CS 3 I Chip select. Digital input active low, used to enable/disable inputs.
DIN 1 I Digital serial data input
OUTA 4 O DAC A analog voltage output
OUTB 7 O DAC B analog voltage output
REF 6 I Analog reference voltage input
SCLK 2 I Digital serial clock input
V
DD
8 P Positive power supply