Datasheet

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      
      
SLAS235B − JULY 1999 − REVISED APRIL 2004
2
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functional block diagram
Serial
Interface
and
Control
8-Bit
DAC
Latch
CS
DIN
OUT
Power-On
Reset
x2
8
2-Bit
Control
Latch
2
Power
and Speed
Control
2
Voltage
Bandgap
PGA With
Output Enable
8
REF
FS
SCLK
Terminal Functions
TERMINAL
I/O/P
DESCRIPTION
NAME NO.
I/O/P
DESCRIPTION
AGND 5 P Ground
CS 3 I Chip select. Digital input active low, used to enable/disable inputs
DIN 1 I Digital serial data input
FS 4 I Frame sync input
OUT 7 O DAC A analog voltage output
REF 6 I/O Analog reference voltage input/output
SCLK 2 I Digital serial clock input
V
DD
8 P Positive power supply