Datasheet

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SLAS152D − DECEMBER 1997 − REVISED APRIL 2004
5
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operating characteristics over recommended operating free-air temperature range (unless
otherwise noted)
analog output dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
s(FS)
Output settling time, full scale
R
L
= 10 k
Ω
,
C
L
= 100 pF,
Fast 3 5.5
s
t
s(FS)
Output settling time, full scale
R
L
= 10 kΩ,
See Note 11
C
L
= 100 pF,
Slow 9 20
µs
t
s(CC)
Output settling time, code to code
R
L
= 10 k
Ω
,
C
L
= 100 pF,
Fast 1 µs
t
s(CC)
Output settling time, code to code
R
L
= 10 kΩ,
See Note 12
C
L
= 100 pF,
Slow 2 µs
SR
Slew rate
R
L
= 10 k
Ω
,
C
L
= 100 pF,
Fast 3.6
V/ s
SR Slew rate
R
L
= 10 kΩ,
See Note 13
C
L
= 100 pF,
Slow 0.9
V/µs
Glitch energy Code transition from 0x7FF to 0x800 10 nV−s
S/N Signal to noise
fs = 400 KSPS fout = 1.1 kHz,
74 dB
S/(N+D) Signal to noise + distortion
fs = 400 KSPS fout = 1.1 kHz,
R
L
= 10 kΩ C
L
= 100 pF,
66 dB
THD Total harmonic distortion
R
L
= 10 k
Ω,
C
L
= 100 pF,
BW = 20 kHz
−68 dB
Spurious free dynamic range
BW = 20 kHz
70 dB
NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of 0x080 to 0x3FF or 0x3FF to 0x080. Not tested, ensured by design.
12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Code change from 0x1FF to 0x200. Not tested, ensured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
digital input timing requirements
MIN NOM MAX UNIT
t
su(CS−FS)
Setup time, CS low before FS↓ 10 ns
t
su(FS−CK)
Setup time, FS low before first negative SCLK edge 8 ns
t
su(C16−FS)
Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising
edge of FS
10 ns
t
su(C16−CS)
Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup
time is between the FS rising edge and CS rising edge.
10 ns
t
wH
Pulse duration, SCLK high 25 ns
t
wL
Pulse duration, SCLK low 25 ns
t
su(D)
Setup time, data ready before SCLK falling edge 8 ns
t
h(D)
Hold time, data held valid after SCLK falling edge 5 ns
t
wH(FS)
Pulse duration, FS high 20 ns