Datasheet

TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
power-on reset
Power-on reset circuitry is available on the TLV5621I. The threshold to trigger a power-on reset is 1.95 V typical
(1.4 V min and 2.5 V max). For a power-on reset, all DACs are shut down. The control register bit values and
states after a power-on reset are listed in Table 5.
Table 5. Control Register Bit Values and States After Power-On Reset
BIT VALUE STATE AFTER POWER-ON RESET
MODE 0 Double buffer mode selected
RNG A 1 Range 2
RNG B 1 Range 2
RNG C 1 Range 2
RNG D 1 Range 2
SIA 0 Shutdown affects DACA according to ACT state
SIB 0 Shutdown affects DACB according to ACT state
SIC 0 Shutdown affects DACC according to ACT state
SID 0 Shutdown affects DACD according to ACT state
ACT 0 DACs in shutdown state